1. A non-volatile memory structure comprising:
a semiconductor substrate;
a transistor structure located on said semiconductor substrate; and
a capacitor structure located on said semiconductor substrate, said capacitor structure having an N-well located in said semiconductor substrate, a pair of regions doped with different type impurities being disposed in said N-well, a first dielectric being disposed on a surface of said N-well, a first conducting gate being disposed on said first dielectric, said transistor structure and said capacitor structure being isolated and electrically connected together as a single floating gate.
2. The non-volatile memory structure as claimed in claim 1, wherein said semiconductor substrate is a p-type semiconductor substrate.
3. The non-volatile memory structure as claimed in claim 1, wherein said two regions doped with different type impurities are an N+-type region and a P+-type region.
4. The non-volatile memory structure as claimed in claim 1, wherein said transistor structure comprises a second dielectric and a second conducting gate, said second dielectric is located on a surface of said semiconductor substrate, said second conducting gate is disposed on said second dielectric, and impurity-doped regions are disposed in said semiconductor substrate and around said second dielectric to be used as a source and a drain, respectively.
5. The non-volatile memory structure as claimed in claim 4, wherein the type of impurity doped in said semiconductor substrate differs from that of said impurity-doped regions.
6. The non-volatile memory structure as claimed in claim 4, wherein the electric connection between said transistor structure and said capacitor structure is accomplished by connecting said first conducting gate and said second conducting gate to be used as a single floating gate.
7. The non-volatile memory structure as claimed in claim 4, wherein said transistor structure and said capacitor structure are isolated by at least an isolator.
8. The non-volatile memory structure as claimed in claim 1, wherein said transistor is a MOSFET.
9. A method for operating a non-volatile memory, said non-volatile memory comprising a transistor structure and a capacitor structure that are isolated from each other on a semiconductor substrate, said transistor structure comprising impurity-doped regions used as a source and a drain, said capacitor structure comprising a pair of regions doped with different type impurities in an N-well, a first dielectric and a first conducting gate being disposed in order on a surface of said N-well, said transistor structure and said capacitor structure being electrically connected together to be used as a single floating gate, said method comprising:
applying a substrate voltage, a source voltage, a drain voltage and a control gate voltage to said semiconductor substrate, said source, said drain and said two regions doped with different type impurities, respectively;
performing a programming step to make said source voltage larger than said substrate voltage so as to generate a wider depleted source-substrate junction; and
performing an erase step to make said control gate voltage larger than said source voltage so as to increase the F-N tunneling current.
10. The method for operating a non-volatile memory as claimed in claim 9, wherein said two regions doped with different type impurities are an N+-type region and a P+-type region.
11. The method for operating a non-volatile memory as claimed in claim 9, wherein in said programming step, a back bias can be extra added to said substrate voltage to make said source voltage larger than said substrate voltage.
12. The method for operating a non-volatile memory as claimed in claim 9, wherein in said programming step, a non-trivial voltage can be extra added to said source voltage to make said source voltage larger than said substrate voltage.
13. The method for operating a non-volatile memory as claimed in claim 9, wherein in said erase step, a small voltage can be extra added to said control gate voltage to make said control gate voltage larger than said source voltage.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A fuel cell stack comprising:
a plurality of fuel cells arranged adjacent one another, at least one fuel cell of said plurality of fuel cells having an electrode plate with a flow field formed therein, a membrane electrode assembly and a compressible fluid-permeable diffusion media disposed between said membrane electrode assembly and said electrode plate; and
a compressing member operable to variably compress said plurality of fuel cells together, said fuel cells being compressed together by said compressing member so that in said at least one fuel cell, a portion of said diffusion media intrudes into said flow field of said adjacent electrode plate.
2. The fuel cell stack of claim 1, wherein said compressing member varies said compression of said fuel cells in response to an operating condition of the fuel cell stack.
3. The fuel cell stack of claim 2, wherein said operating condition is a power output of the fuel cell stack.
4. The fuel cell stack of claim 2, wherein said operating condition is a pressure drop of a feed stream flowing through the fuel cell stack.
5. The fuel cell stack of claim 2, wherein said operating condition is a flow velocity of a feed stream flowing through the fuel cell stack.
6. The fuel cell stack of claim 1, wherein said compressing member comprises a fluid bladder.
7. The fuel cell stack of claim 1, wherein said compressing member comprises a fluid controlled ram.
8. The fuel cell stack of claim 1, wherein said compressing member comprises a mechanically controlled ram.
9. The fuel cell stack of claim 1, wherein said electrode plates are anode plates.
10. The fuel cell stack of claim 1, wherein said electrode plates are cathode plates.
11. A method of operating a fuel cell stack, having a plurality of fuel cells with at least one fuel cell of the plurality of fuel cells having an electrode plate with a flow field formed therein, a membrane electrode assembly (MEA) and fluid-permeable diffusion media disposed between said MEA and said electrode plate, by supplying reactant feed streams to said fuel cell stack; and adjusting a compression of said fuel cell stack in response to an operating condition of said fuel cell stack such that said diffusion media moves relative to said flow field to change the effective flow area thereof.
12. The method of claim 11, further comprising monitoring an operating condition of said fuel cell stack and adjusting said compression of said fuel cell stack in response to said operating condition.
13. The method of claim 12, wherein said monitoring includes monitoring at least one of a power output of said fuel cell stack, a flow rate of a reactant feed stream flowing through said fuel cell stack, and a pressure drop of a reactant feed stream flowing through said fuel cell stack.
14. The method of claim 11, wherein said adjusting includes reducing said compression of said fuel cell stack as a power output of said fuel cell stack increases.
15. The method of claim 11, wherein said adjusting includes increasing said compression of said fuel cell stack as a power output of said fuel cell stack decreases.
16. The method of claim 11, wherein said adjusting includes varying said compression of said fuel cell stack so that a flow velocity of a reactant feed stream flowing through said fuel cell stack is maintained above a predetermined level.
17. The method of claim 11, wherein said adjusting includes varying said compression of said fuel cell stack so that a predetermined pressure drop occurs in a feed stream flowing through said fuel cell stack.
18. The method of claim 17, wherein said predetermined pressure drop is in a range of about 0.1 to about 6 psi.
19. The method of claim 11, wherein said adjusting includes varying a fluid pressure in a bladder that compresses said fuel cell stack.
20. The method of claim 11, wherein said adjusting includes varying a fluid pressure in a ram that compresses said fuel cell stack.
21. The method of claim 11, wherein said adjusting includes varying a mechanical ram that compresses said fuel cell stack.