What is claimed is:
1. A camera that captures an image with an imaging part and displays the image on a displaying device, wherein the camera determines a brightness level of video signals obtained by the imaging part and automatically corrects the video signals according to the determined brightness level and outputs the corrected video signals to the displaying device.
2. A camera comprising:
an imaging part that includes imaging devices;
a signal processing part that processes signals outputted from the imaging part;
a brightness determining part that receives video signals outputted from the signal processing part and determines a brightness level of the received video signals;
a correction amount determining part that determines a correction amount for the video signals according to the brightness level of the video signals determined by the brightness determining part;
a correcting part that corrects the video signals according to the correction amount determined by the correction amount determining part; and
an outputting part that outputs video signals corrected by the correction part to a displaying device.
3. The camera as defined in claim 2 wherein:
the signal processing part comprises an AD converter that converts the signals outputted from the imaging part into digital signals, and a DA converter that converts the video signals corrected by the correcting part into analog signals; and
the correcting part corrects the video signals before the video signals are converted into the analog signals by the DA converter.
4. A camera comprising:
an imaging part that includes imaging devices;
a variable gain amplifier that amplifies signals outputted from the imaging part;
a signal processing part that processes signals amplified by the variable gain amplifier;
a brightness determining part that receives video signals outputted from the signal processing part and determines a brightness level of the received video signals;
a gain controlling part that controls a gain of the variable gain amplifier according to the brightness level of the video signals;
a correction amount determining part that determines a correction amount for the video signals according to the brightness level of the video signals determined by the brightness determining part;
a correcting part that corrects the video signals according to the correction amount determined by the correction amount determining part; and
an outputting part that outputs video signals corrected by the correction part to a displaying device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A MOS circuit for switching an input signal, referenced to a ground, between a signal input terminal and a signal output terminal, comprising:
first and second p-channel transistors formed in an at least one n-conductivity type substrate area and each having a gate, a source connected to the signal input terminal and a drain connected to the signal output terminal;
a comparator for comparing a voltage level at the signal input terminal with ground;
a switch circuit driven by an output of said comparator to selectively connect the at least one n-conductivity type substrate area to the signal input terminal for a positive input voltage level or to the ground for a negative input voltage levels; and
a control circuitry providing gate control signals for the first and second p-channel transistors.
2. The MOS circuit of claim 1, wherein the gate control signals are derived from a clock signal.
3. The MOS circuit of claim 1, wherein the control circuitry comprises a pair of logic gates, each having a first input connected to a signal source, and each having a second input; one of the second inputs being connected to the output of the comparator and another being connected to the output of the comparator through an inverting element.
4. The MOS circuit of claim 3, wherein the switch circuit comprises a first switching transistor with a source connected to the signal input terminal, a drain connected to the at least one n-conductivity type area and a gate connected to the control circuitry; and a second switching transistor with a drain connected to ground, a source connected to the n-conductivity type area and a gate connected to the control circuitry.
5. The MOS circuit of claim 1, wherein the control circuitry has outputs that are capacitively coupled to the p-channel transistor gates.
6. The MOS circuit of claim 3, wherein the pair of logic gates comprises first and second NAND gates; and further comprising a first capacitor connected to the output of the first NAND gate and also to the gate of the first p-channel transistor; and a second capacitor connected to the output of the second NAND gate and also to the gate of the second p-channel transistor.
7. The MOS circuit of claim 4, wherein the control circuitry comprises a third switching transistor selectively connecting the gate of the first p-channel transistor to the signal input terminal; and a fourth switching transistor selectively connecting the gate of the second p-channel transistor to the signal input terminal; the third and fourth switching transistors being controlled in response to the signal source.
8. The MOS circuit of claim 1, wherein the control circuitry comprises a pair of logic gates, a first of the pair of logic gates having an input connected to the output of the comparator; and a second of the pair of logic gates having an input connected to the output of the comparator through an inverting element.
9. A MOS circuit for switching an input signal, referenced to a ground, between a signal input terminal and a signal output terminal, comprising:
a first and second p-channel transistors formed in an at least one n-conductivity type substrate area and each having a gate, a source connected to the signal input terminal and a drain connected to the signal output terminals;
a comparator for comparing a voltage level at the signal input terminal with ground;
a first switch circuit driven by an output of said comparator to selectively connect the at least one n-conductivity type substrate area to the signal input terminal for a positive input voltage level or to ground for a negative input voltage level;
a control circuitry providing gate control signals for the first and second p-channel transistors; wherein the control circuitry comprises a pair of logic gates, a first of the pair of logic gates having an input connected to the output of the comparator; and a second of the pair of logic gates having an input connected to the output of the comparator through an inverting element; wherein the pair of logic gates have outputs that are capacitively coupled to the p-channel transistor gates; and
a second switch circuit driven by a signal source to selectively connect the signal input terminal to each of the gates of the p-channel transistors.