What is claimed is:
1. A method for forming a buried oxide layer in a semiconductor substrate, comprising:
implanting a first dose of oxygen ions in the substrate in a first chamber while maintaining the substrate temperature in a range of about 300 C. to about 600 C.,
implanting a second dose of oxygen ions in the substrate while actively cooling the substrate to maintain the substrate temperature below approximately 150 C., and
annealing the substrate in an oxygen containing atmosphere to generate a buried oxide layer
2. The method of claim 1, wherein the step of implanting a second dose further comprises maintaining the substrate temperature in a range of about 50 C. to about 150 C.
3. The method of claim 1, wherein the annealing step further comprises maintaining the substrate temperature in a range of about 800 C. to about 1400 C.
4. The method of claim 1, wherein the step of implanting a first dose further comprises implanting the oxygen ions in the substrate in a first chamber having a device for heating the substrate.
5. The method of claim 4, wherein the step of implanting a second dose further comprises implanting the oxygen ions in the substrate in a second chamber having a device for actively cooling the substrate.
6. The method of claim 5, wherein the step of annealing the substrate further comprises annealing the substrate in a third chamber.
7. The method of claim 1, wherein the first dose of implanted oxygen ions is selected to be about 1016 to 1018 cm2.
8. The method of claim 1, wherein the second dose of implanted oxygen ions is selected to be approximately 1013 to 51015 cm2.
9. The method of claim 1, wherein the step of implanting a first dose of oxygen ions further comprises bombarding the substrate with oxygen ions having an energy in a range of about 30 keV to about 500 keV.
10. The method of claim 1, wherein the step of implanting a second dose of oxygen ions further comprises conductively cooling the substrate to maintain its temperature below 150 C.
11. The method of claim 10, wherein the step of conductively cooling the substrate further comprises gas cooling the substrate.
12. The method of claim 10, wherein the step of conductively cooling the substrate further comprises utilizing an elastomer to form a conductive thermal path between the substrate and a heat sink.
13. The method of claim 12, further comprising selecting the elastomer to be a silicone resin.
14. The method of claim 1, further comprising selecting the substrate to be any of silicon (Si), germanium (Ge), SiGe alloys.
15. The method of claim 1, further comprising selecting the substrate to be any of a 4-4, 3-5, or 2-6 binary or ternary compound.
16. The method of claim 1, wherein the buried oxide layer has a thickness in a range of about 20 nm to about 500 nm.
17. The method of claim 1, wherein the annealing step is performed while maintaining the substrate temperature in a range of about 800 C. to about 1400 C.
18. The method of claim 14, wherein the annealing step further comprises annealing the substrate for a time period in a range of about 1 hour to about 30 hours.
19. The method of claim 17, wherein the annealing step is performed in an atmosphere having an oxygen concentration in a range of about 1% to 100%.
20. A system for forming a buried oxide layer in a semiconductor substrate, comprising:
a first chamber for implanting a first dose of oxygen ions in the substrate, the first chamber having a heating device for maintaining the substrate temperature in a range of about 300 C. to 600 C. during ion implantation,
a second chamber for implanting a second dose of oxygen ions in the substrate, the second chamber having a cooling device for maintaining the substrate chamber below approximately 150 C. during ion implantation, and
a third chamber for annealing the substrate implanted with ions in the first and second chambers, the third chamber having a heating device capable of maintaining the substrate chamber in a range of about 800 C. to about 1400 C. during annealing.
21. The system of claim 20, wherein the cooling device in the second chamber maintains the substrate temperature in a range of about 50 C. to about 150 C.
22. The system of claim 20, wherein the cooling device conductively cools the substrate.
23. The system of claim 20, wherein the first chamber includes an ion beam apparatus for generating an ion beam having an energy in a selected range.
24. The system of claim 23, wherein the energy of the ion beam is in a range of about 30 keV to about 500 keV.
25. The system of claim 20, wherein the first chamber further comprises an ion guidance device for directing the ion beam onto the substrate.
26. The system of claim 20, wherein each of the chambers includes a holder for holding the substrate.
27. The system of claim 26, wherein the holder in the second chambers functions as a heat sink for removing heat from the substrate.
28. The system of claim 27, wherein the cooling device is coupled to the holder and the substrate and provides a conductive thermal path between the substrate and the holder.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A method for performing clocked operations in an electronic device, the method comprising the steps of:
performing, in a device, first and second operations responsive to a timing clock having a primary frequency f, wherein the device is capable of performing the operations within X and Y cycles of the clock, respectively, and wherein X cycles of the clock correspond to a time interval T1 with the clock operating at the frequency f, and, accordingly, the device is capable of performing XY instances of the second operation within time interval T1 with the clock operating at the frequency f;
generating, during the time interval T1, at least one extra cycle of the clock, to selectively reduce performance time for the first operation; and
masking a certain effect of the at least one extra cycle for the second operation, so that instances of the second operation during the interval T1 remain no greater in number than XY.
2. The method of claim 1, wherein a first clock signal has frequency f and a second clock signal has a frequency greater than f, and wherein generating the least one extra cycle comprises selecting, during some of the time T1, the second clock signal for output as the timing clock.
3. The method of claim 2, wherein instances of the second operation are initiated by asserting an operation-initiating control signal in conjunction with asserting the timing clock, and wherein masking the effect of the a least one extra cycle comprises altering timing of the control signal, so that assertion of the control signal occurs during a different time interval than does assertion of the extra clock cycle.
4. The method of claim 2, wherein a third clock signal has a frequency greater than the frequency of the second clock signal, the method comprising clocking a state machine by the third clock signal.
5. The method of claim 4, wherein initiating the at least one extra cycle includes asserting an extra-clock-cycle-initiating control signal as an input to the state machine.
6. The method of claim 4, the method comprising clocking an output register by the third clock signal.
7. The method of claim 6, wherein initiating the least one extra cycle includes asserting an extra-clock-cycle-initiating control signal as an input to the output register.
8. The method of claim 4, wherein an output register outputs the timing clock responsive to output signals of the state machine.
9. The method of claim 8, wherein the output register outputs a mask signal for masking the certain effect of the extra cycle responsive to output signals of the state machine.
10. An apparatus for performing clocked operations comprising:
first circuitry for performing first and second operations responsive to a timing clock having a primary frequency f, wherein the first circuitry is capable of performing the operations within X and Y cycles of the clock, respectively, and wherein X cycles of the clock correspond to a time interval T1 with the clock operating at the frequency f, and, accordingly, the first circuitry is capable of performing XY instances of the second operation within time interval T1 with the clock operating at the frequency f; and
second circuitry for generating, during the time interval T1, at least one extra cycle of the clock, to reduce performance time for the first operation, and for masking an affect of the at least one extra cycle with respect to the second operation, so that instances of the second operation during the interval T1 remain no greater in number than XY.
11. The apparatus of claim 10, wherein a first clock signal has frequency f and a second clock signal has a frequency greater than f, and wherein the second circuitry comprises circuitry for selecting, during some of the time T1, the second clock signal for output as the timing clock.
12. The apparatus of claim 11, wherein the first circuitry is operable to initiate instances of the second operation responsive to an operation-initiating-control signal asserted in conjunction with the timing clock, and wherein the second circuitry is operable to alter timing of the control signal, so that assertion of the control signal occurs during a different time interval than does assertion of the extra clock cycle.
13. The apparatus of claim 11, wherein a third clock signal has a frequency greater than the frequency of the second clock signal, and the second circuitry comprises a state machine clocked by the third clock signal.
14. The apparatus of claim 13, wherein the second circuitry is operable to initiate the at least one extra cycle responsive to an extra-clock-cycle-initiating control signal input to the state machine.
15. The apparatus of claim 13, wherein the second circuitry comprises an output register clocked by the third clock signal.
16. The apparatus of claim 15, wherein the second circuitry is operable to initiate the at least one extra cycle responsive to an extra-clock-cycle-initiating control signal input to the output register.
17. The apparatus of claim 13, wherein the second circuitry comprises an output register operable to output the timing clock responsive to output signals of the state machine.
18. The apparatus of claim 17, wherein the output register is operable to output a mask signal for masking the certain effect of the extra cycle responsive to output signals of the state machine.
19. A computer program product for performing clocked operations in an electronic device, wherein the device is operable to perform first and second operations responsive to a timing clock having a primary frequency f, the device being capable of performing the operations within X and Y cycles of the clock, respectively, and wherein X cycles of the clock correspond to a time interval T1 with the clock operating at the frequency f, and, accordingly, the device is capable of performing XY instances of the second operation within time interval T1 with the clock operating at the frequency f, the computer program product comprising:
first instructions for generating, during the time interval T1, at least one extra cycle of the clock, to selectively reduce performance time for the first operation; and
second instructions for masking a certain effect of the at least one extra cycle for the second operation, so that instances of the second operation during the interval T1 remain no greater in number than XY.
20. The computer program product of claim 19, wherein a first clock signal has frequency f and a second clock signal has a frequency greater than f, and wherein first instructions for generating the least one extra cycle comprise instructions for selecting, during some of the time T1, the second clock signal for output as the timing clock.
21. The computer program product of claim 20, wherein instances of the second operation are initiated in the device by asserting an operation-initiating control signal in conjunction with asserting the timing clock, and wherein the second instructions comprise instructions for altering timing of the control signal, so that assertion of the control signal occurs during a different time interval than does assertion of the extra clock cycle.