What is claimed is:
1. A method of manufacturing a semiconductor device, comprising the steps of:
(a) preparing a substrate having a surface in which a first trench for use as an alignment mark is formed and on which a first film is formed, avoiding said first trench;
(b) forming a second film on side and bottom surfaces of said first trench; and
(c) selectively etching said first film using said second film as a protective film.
2. The method according to claim 1, wherein
said step (b) includes the steps of:
(b-1) forming an insulation film on a whole surface of said substrate to fill said first trench with said insulation film; and
(b-2) selectively etching said insulation film to partially remove said insulation film in said first trench and to leave said insulation film on said side and bottom surfaces of said first trench, and
said second film is said insulation film which remains in said first trench after execution of said step (b-2).
3. The method according to claim 2, wherein
etching performed in said step (b-2) is anisotropic etching.
4. The method according to claim 1, wherein
said step (b) includes the steps of:
(b-1) forming an insulation film on a whole surface of said substrate to fill said first trench with said insulation film;
(b-2) selectively etching said insulation film to expose said side and bottom surfaces of said first trench; and
(b-3) forming a second insulation film on said side and bottom surfaces of said first trench, and
said second film is said second insulation film.
5. The method according to claim 4, wherein
said first trench formed in said surface of said substrate prepared in said step (a) includes a plurality of first trenches, and
in said step (b-3), said second insulation film is formed by oxidation of said substrate on said side and bottom surfaces of each of said first trenches.
6. The method according to claim 2, wherein
in said surface of said substrate prepared in said step (a), a second trench is further formed, which forms an element isolation structure and partitions off an active region of said substrate,
in said step (b-1), said insulation film is formed on the whole surface of said substrate to also fill said second trench with said insulation film, and
in said step (b-2), said insulation film is selectively etched to further remove said insulation film on said active region partitioned off by said second trench.
7. The method according to claim 4, wherein
in said surface of said substrate prepared in said step (a), a second trench is further formed, which forms an element isolation structure and partitions off an active region of said substrate,
in said step (b-1), said insulation is formed on the whole surface of said substrate to also fill said second trench with said insulation film, and
in said step (b-2), said insulation film is selectively etched to further remove said insulation film on said active region partitioned off by said second trench.
8. The method according to claim 6, wherein
said element isolation structure is used as an alignment mark.
9. The method according to claim 7, wherein
said element isolation structure is used as an alignment mark.
10. A method of manufacturing a semiconductor device, comprising the steps of:
(a) preparing a substrate, in a surface of which a trench for use as an alignment mark is formed;
(b) forming a gate electrode material on said substrate to cover said trench; and
(c) selectively etching said gate electrode material while leaving said gate electrode material formed on said trench, to selectively form a gate structure on said substrate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of characterizing a communications channel within a high speed memory system, comprising:
generating a first signal having a simple, known, repeating pattern;
generating a second signal having a pseudo-random pattern;
combining said first and second signals to produce a combined signal having a large number of signal transitions;
transmitting said combined signal from a processor to a memory device over a bus of a memory system;
receiving said combined signal;
removing said second signal from said received combined signal to produce a received first signal; and
comparing a signal pattern of said received first signal to said simple, known, repeating pattern.
2. The method of claim 1 wherein said combining includes an exclusive OR operation.
3. The method of claim 2 wherein said removing includes an exclusive OR operation.
4. The method of claim 1 wherein said pseudo-random pattern includes an x\u22121+x\u22124 pattern.
5. The method of claim 1 additionally comprising adjusting said transmitting in response to said comparing.
6. The method of claim 1 additionally comprising adjusting said receiving in response to said comparing.
7. A method of characterizing a communications channel within a high speed memory system, comprising:
generating a first signal having a simple, known, repeating pattern;
generating a second signal having a pseudo-random pattern;
encoding said first signal with said second signal to produce a coded signal having a large number of signal transitions;
transmitting said coded signal from a processor to a memory device over a bus of a memory system;
receiving said coded signal;
generating a third signal having the same pseudo-random pattern as said second signal;
decoding said received coded signal with said third signal to recover a received first signal; and
examining the pattern of said received first signal.
8. The method of claim 7 wherein said encoding includes an exclusive OR operation.
9. The method of claim 8 wherein said decoding includes an exclusive OR operation.
10. The method of claim 7 wherein said pseudo-random pattern includes an x\u22121+x\u22124 pattern.
11. The method of claim 7 additionally comprising adjusting said transmitting in response to said examining.
12. The method of claim 7 additionally comprising adjusting said receiving in response to said examining.
13. A method of determining the transmission characteristics of a communications channel within a high speed memory system, comprising at a transmitting location:
generating a first signal having a simple, known, repeating pattern;
generating a second signal having a pseudo-random pattern;
combining said first and second signals through an exclusive OR operation to produce a combined signal having a large number of signal transitions;
transmitting said combined signal from a processor to a memory device over a bus of a memory system;
and further comprising at a receiving location:
receiving said combined signal;
generating a third signal having the same pseudo-random pattern as said second signal;
combining said received combined signal and said third signal through an exclusive OR operation to produce a received first signal; and
comparing a signal pattern of said received first signal to said simple, known, repeating pattern.
14. The method of claim 13 wherein said pseudo-random pattern includes an x\u22121+x\u22124 pattern.
15. The method of claim 13 additionally comprising adjusting said transmitting in response to said comparing.
16. The method of claim 13 additionally comprising adjusting said receiving in response to said comparing.
17. An apparatus for characterizing a communications channel within a high speed memory system, comprising at a transmitting location:
a generator for generating a first signal having a simple, known repeating pattern;
a generator for generating a second signal having a pseudo-random pattern;
a first circuit for combining said first and second signals to produce a combined signal having a large number of signal transitions;
a transmitter for transmitting said combined signal from a processor to a memory device over a bus of a memory system, and comprising at a receiving location;
a receiver for receiving said combined signal;
a second circuit for removing said second signal from said received combined signal to produce a received first signal; and
a circuit for examining the pattern of said received first signal.
18. The apparatus of claim 17 wherein said first circuit includes an exclusive OR gate.
19. The apparatus of claim 18 wherein said second circuit includes an exclusive OR gate.
20. The apparatus of claim 17 wherein said generator for generating a second signal produces a second signal having a pseudo-random pattern including an x\u22121+x\u22124 pattern.
21. The apparatus of claim 17 wherein transmission parameters of said transmitter are adjusted in response to said circuit for examining.
22. The apparatus of claim 17 wherein reception parameters of said receiver are adjusted in response to said circuit for examining.
23. A memory system of the type having a memory controller communicating with a plurality of memory devices through a communications channel, characterized in that said memory controller comprises:
a generator for generating a first signal having a simple, known, repeating pattern;
a generator for generating a second signal having a pseudo-random pattern;
a first circuit for combining said first and second signals to produce a combined signal having a large number of signal transitions;
a transmitter for transmitting said combined signal over a bus of a memory system, said memory system further characterized in that each of said memory devices comprises;
a receiver for receiving said combined signal;
a second circuit for removing said second signal from said received combined signal to produce a received first signal; and
a circuit for examining the pattern of said received first signal.
24. The system of claim 23 wherein said first circuit includes an exclusive OR gate.
25. The system of claim 24 wherein said second circuit includes an exclusive OR gate.
26. The system of claim 23 wherein said generator for producing a second signal produces a second signal having a pseudo-random pattern including an x\u22121+x\u22124 pattern.
27. The system of claim 23 wherein said transmitter is responsive to said circuit for examining.
28. The system of claim 23 wherein said receiver is responsive to said circuit for examining.