1. A method of communicating between a media access control layer (MAC) and a physical layer (PHY), comprising:
receiving a first time-division multiplexed signal on a receive data pin;
receiving a plurality of time-division multiplexed receive control signals on a single receive control pin;
sending a second time-division multiplexed signal on a transmit data pin;
sending a plurality of time-division multiplexed transmit control signals on a single transmit control pin,
wherein the receive control signals include a receive data valid signal and a receive error signal time-division multiplexed together on the single receive control pin and the transmit control signals include a synchronization (SYNC) signal a transmit enable signal and a transmit error signal time-division multiplexed together on the single transmit control pin.
2. The method of claim 1 wherein the time-division multiplexed receive control signals includes a plurality of 4 bit segments and wherein each 4 bit segment includes a synchronization bit.
3. The method of claim 2 wherein the beginning of each 4 bit segment of the receive control signals is determined by the synchronization bit of such each 4 bit segment.
4. The method of claim 1 wherein the time-division multiplexed receive control signals includes a plurality of 4 bit segments and wherein each 4 bit segment includes a receive data valid bit.
5. The method of claim 1 wherein the time-division multiplexed receive control signals includes 4 bit segments and wherein each 4 bit segment includes a receive error bit.
6. The method of claim 1 wherein the time-division multiplexed receive control signals includes a plurality of 4 bit segments and wherein each 4 bit segment includes a carrier sense bit.
7. The method of claim 1 when the time-division multiplexed transmit control signals includes a plurality of 4 bit segments and wherein each 4 bit segment includes a synchronization bit.
8. The method of claim 7 where the beginning of each 4 bit segment is determined by the synchronization bit of such each 4 bit segment.
9. The method of claim 1 wherein the time-division multiplexed transmit control signals includes a plurality of 4 bit segments and wherein each 4 bit segment includes a transmit enable bit.
10. The method of claim 1 wherein the time-division multiplexed transmit control signals includes a plurality of 4 bit segments and wherein each 4 bit segment includes a transmit error bit.
11. The method of claim 1 further including indicating the peed of the PHY using the receive data pin.
12. The method of claim 11 wherein indicating the speed of the PHY using the receive data pin includes including an interface speed bit in a data segment when a receive control segment indicates no carrier sense, no receive data valid and no receive error.
13. The method of claim 1 further including buffering data transmitted from the PHY to the MAC using an elasticity buffer that is at least 27 bits long.
14. The method of claim 1 further including buffering data transmitted from the PHY to the MAC using an elasticity buffer that long enough to buffer an entire frame of data from a data source having a clock with a frequency tolerance of 0.1%.
15. An interface between a first media access control layer and a second media access control layer, comprising:
a time-division multiplexed receive data pin;
a time-division multiplexed receive control pin for receiving different functional types of receive control signals including a receive data valid signal and a receive error signal that are time-division multiplexed together on the receive control pin;
a time-division multiplexed transmit data pin; and
a time-division multiplexed transmit control pin for transmitting different functional types of transmit control signals including a synchronization (SYNC) signal, a transmit enable signal and transmit error signal that are time-division multiplexed together on the transmit control pin.
16. A media access control layer to physical layer interface comprising:
a common clock;
a time-division multiplexed receive data pin;
a time-division multiplexed receive control pin for receiving different functional types of receive control signals including a receive data valid signal and a receive error signal time-division multiplexed together on the receive control pin;
a time-division multiplexed transmit data pin;
a time-division multiplexed transmit control pin for transmitting different functional types of transmit control signals including a synchronization (SYNC) signal, a transmit enable signal and a transmit error signal time-division multiplexed together on the transmit control pin.
17. The interface of claim 16, wherein said time-division multiplexed receive control pin contains receive control signals further comprising a carrier sense signal and a synchronization (SYNC) signal.
18. The method of claim 1, wherein the receive control signals further include a synchronization (SYNC) gal and a carrier sense signal.
19. The interface of claim 15, wherein the receive control signals include a plurality of 4 bit segments and wherein each 4 bit segment includes a synchronization bit.
20. The interface of claim 19 wherein the beginning of each 4 bit segment of the receive control signals is determined by the synchronization bit of such each 4 bit segment.
21. The interface of claim 15 wherein the receive control signals include a plurality of 4 bit segments and wherein each 4 bit segment includes a receive data valid bit.
22. The interface of claim 15 wherein the receive control signals includes 4 bit segments and wherein each 4 bit segment includes a receive error bit.
23. The interface of claim 15 wherein the receive control signals includes a plurality of 4 bit segments and wherein each 4 bit segment includes a carrier sense bit.
24. The interface of claim 15 wherein the trait control signals includes a plurality of 4 bit segments and wherein each 4 bit segment includes a synchronization bit.
25. The interface of claim 24 wherein the beginning of each 4 bit segment is determined by the synchronization bit of such each 4 bit segment.
26. The interface of claim 15 wherein the transmit control signals includes a plurality of 4 bit segments and where each 4 bit segment includes a transmit enable bit.
27. The interface of claim 15 wherein the transmit control signals includes a plurality of 4 bit segments and wherein each 4 bit segment includes a transmit error bit.
28. The interface of claim 15 wherein the receive data pin is further arranged to indicate the speed of the PRY.
29. The interface of claim 28 wherein the receive data pin is arranged to indicate the speed of the PHY by including an interface speed bit in a data segment when a receive control segment indicates no carrier sense, no receive data valid and no receive error.
30. The interface of claim 15 further comprising an elasticity buffer that is at least 27 bits long for buffering data transmitted from the PHY to the MAC.
31. The interface of claim 15 further including an elasticity buffer that is long enough to buffer an entire frame of data from a data source hang a clock with a frequency tolerance of 0.1% and is arranged to buffer data transmitted from the PHY to the MAC.
32. The interface of claim 15, wherein the receive control signals further include a synchronization (SYNC) signal and a carrier sense signal.
33. An apparatus communicating between a media access control layer (MAC) and a physical layer (PHY), comprising:
means for receiving a first time-division multiplexed signal on a receive data pin;
means for receiving a plurality of time-division multiplexed receive control signals on a single receive control pin;
means for sending a second time-division multiplexed signal on a transmit data pin;
means for sending a plurality of time-division multiplexed it control signals on a single transmit control pin,
wherein the receive control signals include a receive data valid signal and a receive error signal time-division multiplexed together on the single receive control pin and the transmit control signals include a synchronization (SYNC) signal, a transmit enable signal and a transmit error signal time-division multiplexed together on the single transmit control pin.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of self-reference reading a spin-transfer torque memory unit, comprising:
applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a first resistance state, the magnetic tunnel junction comprising a free magnetic layer having a free magnetization orientation and a reference magnetic layer having a reference magnetization orientation, the magnetic tunnel junction data cell having a first energy barrier value required to switch the magnetic tunnel junction data cell between a high resistance state and a low resistance state;
storing the first bit line read voltage in a first voltage storage device;
applying a first magnetic field through the magnetic tunnel junction data cell forming a magnetic field modified magnetic tunnel junction data cell, the magnetic field being parallel or anti-parallel with the magnetization orientation of the reference magnetic layer, the magnetic field modified magnetic tunnel junction data cell having a second energy barrier value being greater than the first energy barrier value;
applying a second read current thorough the magnetic field modified magnetic tunnel junction data cell having the first resistance state and forming a second bit line read voltage, the first read current being less than the second read current;
storing the second bit line read voltage in a second voltage storage device; and
comparing the stored first bit line read voltage with the stored second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.
2. A method according to claim 1, wherein the storing step comprises storing the second bit line read voltage in a second voltage storage device and a third voltage storage device, the second voltage storage device and the third voltage storage device are electrically connected in series.
3. A method according to claim 1, wherein the comparing step comprises comparing the stored first bit line read voltage with the stored second bit line read voltage and if the stored first bit line read voltage is substantially the same as or less than the stored second bit line read voltage, then the first resistance state is determined to be a low resistance state.
4. A method according to claim 1, wherein the comparing step comprises comparing the stored first bit line read voltage with the stored second bit line read voltage and if the stored first bit line read voltage is greater than or not substantially the same as the stored second bit line read voltage, then the first resistance state is determined to be a high resistance state.
5. A method according to claim 1, wherein the comparing step comprises comparing the stored first bit line read voltage with the stored second bit line read voltage and if the stored first bit line read voltage is 25% greater than the stored second bit line read voltage then the first resistance state is determined to be a high resistance state.
6. A method according to claim 1, wherein the applying a magnetic field through the magnetic tunnel junction data cell comprises generating a magnetic field by passing a current through a wire, the wire being adjacent to the magnetic tunnel junction data cell.
7. A method according to claim 1, wherein the first read current is 10% to 50% of the second read current.
8. A method according to claim 1, wherein the applying a first read current step occurs without applying a magnetic field through the magnetic tunnel junction data cell.
9. A method according to claim 1, wherein the applying a first read current step occurs while applying a second magnetic field through the magnetic tunnel junction data cell, the second magnetic field being parallel or anti-parallel with the magnetization orientation of the reference magnetic layer, and the second magnetic field having an equal magnitude to the first magnetic field.
10. A method according to claim 1, wherein the applying a first read current step occurs while applying a second magnetic field through the magnetic tunnel junction data cell, the second magnetic field being parallel or anti-parallel with the magnetization orientation of the reference magnetic layer, and the second magnetic field having a different magnitude than the first magnetic field.
11. A method of writing to a spin-transfer torque memory unit, comprising:
applying a magnetic field through magnetic tunnel junction data cell, forming a magnetic field modified magnetic tunnel junction data cell, the magnetic tunnel junction data cell having an energy barrier value required to switch the magnetic tunnel junction data cell between a high resistance state and a low resistance state, the magnetic field being parallel or anti-parallel with a magnetization orientation of a reference magnetic layer of the magnetic tunnel junction data cell, and the magnetic field decreases the energy barrier value required to switch the magnetic tunnel junction data cell between a high resistance state and a low resistance state; and
applying a write current through the magnetic field modified magnetic tunnel junction data cell to switch the magnetic field modified magnetic tunnel junction data cell between a high resistance state and low resistance state.
12. A method according to claim 11, wherein the applying a magnetic field step comprises generating a magnetic field by passing a current through a wire, the wire being adjacent to the magnetic tunnel junction data cell.
13. A method according to claim 11, wherein the applying a magnetic field step reduces a switching current required to switch the magnetic field modified magnetic tunnel junction data cell between a high resistance state and low resistance state as compared to a method without the applying a magnetic field step.
14. A method according to claim 11, wherein the applying a magnetic field step reduces a time duration required to switch the magnetic field modified magnetic tunnel junction data cell between a high resistance state and low resistance state as compared to a method without the applying a magnetic field step.
15. A method according to claim 11, wherein the write current is a polarized write current.
16. A method according to claim 11, wherein the magnetic field formed in a first direction through the magnetic tunnel junction data cell assists in switching the magnetic tunnel junction data cell from a low resistance state to a high resistance state and the magnetic field formed in a second direction, opposing the first direction, through the magnetic tunnel junction data cell assists in switching the magnetic tunnel junction data cell from a high resistance state to a low resistance state.
17. A spin-transfer torque memory apparatus comprising:
a magnetic tunnel junction data cell comprising a magnetic free layer and a magnetic reference layer separated by a oxide barrier layer, the magnetic tunnel junction data cell electrically between a bit line and a source line, the magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell;
an adjustable current driver electrically coupled to the bit line, the adjustable current driver configured to provide a provide a first read current and a second read current through the magnetic tunnel junction data cell;
a magnetic field generator adjacent to the magnetic tunnel junction data cell;
a first voltage storage device electrically coupled to the bit line and configured to store a first bit line voltage formed by the first read current;
a second voltage storage device electrically coupled to the bit line and configured to store a second bit line voltage formed by the second read current;
a third voltage storage device electrically coupled to the bit line and configured to store a second bit line voltage formed by the second read current, the second voltage storage device and the third voltage storage device are electrically connected in series; and
a differential sense amplifier electrically coupled to the first voltage storage device and electrically coupled to an intermediate node electrically between the second voltage storage device and the third voltage storage device, the differential sense amplifier configured to compare the first bit line voltage with the second bit line voltage.
18. A spin-transfer torque memory apparatus according to claim 17, the magnetic field generator generators a magnetic field through the magnetic tunnel junction data cell, the magnetic field being parallel or anti-parallel with a magnetization orientation of a reference magnetic layer of the magnetic tunnel junction data cell.
19. A spin-transfer torque memory apparatus according to claim 17, wherein the magnetic field generator comprises an electrically conductive wire.