1. A vehicular seat belt system comprising a takeout hole for pulling a seat belt out of a seal belt retractor provided on a vehicle body into a cabin side is formed in a cabin trim the seat belt is located near a part mounting hole formed in said cabin trim, and a slit is formed so as to connect said part mounting hole to said takeout hole for the seat belt, wherein said takeout hole for pulling out said seat belt is formed in said cabin trim at a height position approximately equal to the lower end portion of said part mounting hole and on the rear side of said part mounting hole formed in said cabin trim, and the rear portion of said part mounting hole is connected to the front portion of said takeout hole by said slit.
2. The vehicular seat belt system according to claim 1, wherein a notch portion for expanding the opening portion of said slit is formed at the opening end of said slit formed in said part mounting hole.
3. The vehicular seat belt system according to claim 2, wherein a slanting face expanding toward the opening side is formed on the lower end side of said notch portion.
4. The vehicular seat belt system according to claim 1, wherein claws are projectingly provided in the peripheral portion of said part cover as an engagement portion so as to be directed toward said part mounting hole, and, of said fixing portions provided around said part mounting hole, the fixing portions on both sides of said slit have a thickness larger than that of other fixing portions.
5. The vehicular seat belt system according to claim 1, wherein claws are projectingly provided in the peripheral portion of said part cover as an engagement portion so as to be directed toward said part mounting hole, and the thickness of said part cover in the base portion of the claw engaging with the fixing portion formed on both sides of said slit is larger than that of other portions.
6. The vehicular seat belt system according to claim 1, wherein claws are projectingly provided in the peripheral portion of said part cover as an engagement portion so as to be directed toward said part mounting hole, and padding is provided on the claw engaging with the fixing portion formed on both sides of said slit to fill the gap between the fixing portion provided around the part mounting hole and the peripheral portion of said part mounting hole.
7. A vehicular seat belt system comprising a takeout hole for pulling a seat belt out of a seat belt retractor provided on a vehicle body into the cabin side is formed in a cabin trim, wherein said takeout hole for the seat belt is formed near a part mounting hole formed in said cabin trim; a slit is formed so as to connect said part mounting hole to said takeout hole for the seat belt; a plurality of fixing portions for installing a part cover for closing said part mounting hole are formed in the peripheral portion of said part mounting hole; and some of said fixing portions are formed on both sides of said slit.
8. A vehicular seat belt system comprising a takeout hole for pulling a seat belt out of a seat belt retractor provided on a vehicle body into the cabin side is formed in a cabin trim, wherein said takeout hole for the seat belt is located near an other part mounting hole formed in said cabin trim; a slit is formed so as to connect said other part mounting hole to said takeout hole for the seat belt; and said slit is covered with an other part cover.
9. The system of claim 8 wherein said other part cover is a speaker cover.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit, comprising:
a substrate;
an n-channel metal oxide semiconductor (NMOS) transistor located in and on said substrate, said NMOS transistor including:
an NMOS gate located on an NMOS gate dielectric layer on said substrate, said NMOS gate including polysilicon;
sidewall spacers abutting said NMOS gate, said sidewall spacers including dielectric material;
n-type n-channel sourcedrain (NSD) layers in said substrate adjacent to said NMOS gate, said NSD layers containing n-type dopants;
a p-channel metal oxide semiconductor (PMOS) transistor located in and on said substrate, said PMOS transistor including:
a PMOS gate located on a PMOS gate dielectric layer on said substrate, said PMOS gate including polysilicon;
sidewall spacers abutting said PMOS gate, said sidewall spacers including dielectric material;
p-type p-channel sourcedrain (PSD) layers in said substrate adjacent to said PMOS gate, said PSD layers containing p-type dopants;
a counterdoped polysilicon gate material resistor located over said substrate; said counterdoped polysilicon gate material resistor including:
a resistor layer, said resistor layer including polysilicon, said resistor layer having a body region containing n-type dopants as located in said NSD layers and p-type dopants as located in said PSD layers, and said resistor layer having head regions at each end of said body region, said head regions having a same conductivity type as said body region;
a resistor silicide block layer located over said body region, said resistor silicide block layer including different dielectric material than said sidewall spacers; and
silicide layers on said head regions, said NSD layers and said PSD layers; and
a pre-metal dielectric (PMD) layer located over said silicide layers and said resistor silicide block layer.
2. The integrated circuit of claim 1, in which said resistor silicide block layer includes silicon dioxide.
3. The integrated circuit of claim 1, in which:
said body region of said resistor layer is p-type; and
said head regions of said resistor layer are p-type.
4. The integrated circuit of claim 3, in which an average density of p-type dopants in said head regions of said resistor layer is at least 10 percent greater than an average density of p-type dopants in said body region of said resistor layer.
5. A process of forming an integrated circuit, comprising the steps:
providing a substrate;
forming a gate dielectric layer on said substrate;
forming a gate polysilicon layer over said substrate and said gate dielectric layer;
etching said gate polysilicon layer to form:
an NMOS gate and a PMOS gate on said gate dielectric layer; and
a resistor layer, said resistor layer having a body region and having head regions at each end of said body region;
forming sidewall spacers abutting said NMOS gate and abutting said PMOS gate;
forming an NSD implant mask over said substrate which:
exposes said NMOS gate and said substrate adjacent to said NMOS gate;
exposes said body region of said resistor layer; and
covers said PMOS gate and said substrate adjacent to said PMOS gate
performing an NSD implant operation which implants n-type dopants into said substrate adjacent to said NMOS gate to form NSD layers and into said body region of said resistor layer;
forming a PSD implant mask over said substrate which:
exposes said PMOS gate and said substrate adjacent to said PMOS gate;
exposes said body region of said resistor layer; and
covers said NMOS gate and said substrate adjacent to said NMOS gate
performing a PSD implant operation which implants p-type dopants into said substrate adjacent to said PMOS gate to form PSD layers and into said body region of said resistor layer;
forming a resistor silicide block layer over said body region of said resistor layer, such that said resistor silicide block layer includes different dielectric material than said sidewall spacers;
forming metal silicide layers on said head regions of said resistor layer, on said NSD layers adjacent to said NMOS gate, and on said PSD layers adjacent to said PMOS gate;
forming a PMD layer over said silicide layers and over said resistor silicide block layer; and
forming contacts through said PMD layer, said contacts making electrical connection to said silicide layers on said NSD layers and to said silicide layers on said PSD layers.
6. The process of claim 5, in which said resistor silicide block layer includes silicon dioxide.
7. The process of claim 5, further including steps:
forming an n-channel lightly doped drain (NLDD) implant mask over said substrate, after said step of etching said gate polysilicon layer and prior to said step of forming said sidewall spacers, which:
exposes said NMOS gate and said substrate adjacent to said NMOS gate;
covers said body region of said resistor layer; and
covers said PMOS gate and said substrate adjacent to said PMOS gate;
performing an NLDD implant operation which implants n-type dopants into said substrate adjacent to said NMOS gate to form NLDD layers;
forming a p-channel lightly doped drain (PLDD) implant mask over said substrate, after said step of etching said gate polysilicon layer and prior to said step of forming said sidewall spacers, which:
exposes said PMOS gate and said substrate adjacent to said PMOS gate;
covers said body region of said resistor layer; and
covers said NMOS gate and said substrate adjacent to said NMOS gate; and
performing a PLDD implant operation which implants p-type dopants into said substrate adjacent to said PMOS gate to form PLDD layers.
8. The process of claim 7, in which:
said NLDD implant mask covers said head regions of said resistor layer; and
said PLDD implant mask covers said head regions of said resistor layer.
9. The process of claim 7, in which:
said body region of said resistor layer is p-type;
said head regions of said resistor layer are p-type;
said NLDD implant mask covers said head regions of said resistor layer;
said PLDD implant mask covers said head regions of said resistor layer;
said NSD implant mask covers said head regions of said resistor layer; and
said PSD implant mask exposes said head regions of said resistor layer so that said PSD implant operation implants p-type dopants into said head regions.
10. The process of claim 7, in which:
said body region of said resistor layer is n-type;
said head regions of said resistor layer are n-type;
said NLDD implant mask covers said head regions of said resistor layer;
said PLDD implant mask covers said head regions of said resistor layer;
said NSD implant mask exposes said head regions of said resistor layer so that said NSD implant operation implants n-type dopants into said head regions; and
said PSD implant mask covers said head regions of said resistor layer.
11. The process of claim 7, in which:
said body region of said resistor layer is p-type;
said head regions of said resistor layer are p-type;
said NLDD implant mask covers said head regions of said resistor layer;
said PLDD implant mask exposes said head regions of said resistor layer so that said PLDD implant operation implants p-type dopants into said head regions;
said NSD implant mask exposes said head regions of said resistor layer so that said NSD implant operation implants n-type dopants into said head regions; and
said PSD implant mask exposes said head regions of said resistor layer so that said PSD implant operation implants p-type dopants into said head regions.
12. The process of claim 7, in which:
said body region of said resistor layer is n-type;
said head regions of said resistor layer are n-type;
said NLDD implant mask exposes said head regions of said resistor layer so that said NLDD implant operation implants n-type dopants into said head regions;
said PLDD implant mask covers said head regions of said resistor layer;
said NSD implant mask exposes said head regions of said resistor layer so that said NSD implant operation implants n-type dopants into said head regions; and
said PSD implant mask exposes said head regions of said resistor layer so that said PSD implant operation implants p-type dopants into said head regions.
13. The process of claim 7, in which:
said body region of said resistor layer is p-type;
said head regions of said resistor layer are p-type;
said NLDD implant mask covers said head regions of said resistor layer;
said PLDD implant mask exposes said head regions of said resistor layer so that said PLDD implant operation implants p-type dopants into said head regions;
said NSD implant mask covers said head regions of said resistor layer; and
said PSD implant mask exposes said head regions of said resistor layer so that said PSD implant operation implants p-type dopants into said head regions.
14. The process of claim 5, further including steps:
forming an n-channel lightly doped drain (NLDD) implant mask over said substrate, after said step of etching said gate polysilicon layer and prior to said step of forming said sidewall spacers, which:
exposes said NMOS gate and said substrate adjacent to said NMOS gate;
exposes said body region of said resistor layer; and
covers said PMOS gate and said substrate adjacent to said PMOS gate;
performing an NLDD implant operation which implants n-type dopants into said substrate adjacent to said NMOS gate to form NLDD layers and into said body region;
forming a p-channel lightly doped drain (PLDD) implant mask over said substrate, after said step of etching said gate polysilicon layer and prior to said step of forming said sidewall spacers, which:
exposes said PMOS gate and said substrate adjacent to said PMOS gate;
covers said body region of said resistor layer; and
covers said NMOS gate and said substrate adjacent to said NMOS gate; and
performing a PLDD implant operation which implants p-type dopants into said substrate adjacent to said PMOS gate to form PLDD layers.
15. The process of claim 5, further including steps:
forming an n-channel lightly doped drain (NLDD) implant mask over said substrate, after said step of etching said gate polysilicon layer and prior to said step of forming said sidewall spacers, which:
exposes said NMOS gate and said substrate adjacent to said NMOS gate;
covers said body region of said resistor layer; and
covers said PMOS gate and said substrate adjacent to said PMOS gate;
performing an NLDD implant operation which implants n-type dopants into said substrate adjacent to said NMOS gate to form NLDD layers;
forming a p-channel lightly doped drain (PLDD) implant mask over said substrate, after said step of etching said gate polysilicon layer and prior to said step of forming said sidewall spacers, which:
exposes said PMOS gate and said substrate adjacent to said PMOS gate;
exposes said body region of said resistor layer; and
covers said NMOS gate and said substrate adjacent to said NMOS gate; and
performing a PLDD implant operation which implants p-type dopants into said substrate adjacent to said PMOS gate to form PLDD layers and into said body region.
16. The process of claim 5, further including steps:
forming an n-type pre gate etch implant mask over said substrate, after said step of forming said gate polysilicon layer and prior to said step of etching said gate polysilicon layer, which:
exposes an area for said NMOS gate;
exposes an area for said body region of said resistor layer; and
covers an area for said PMOS gate; and
performing an n-type pre gate etch implant operation which implants n-type dopants into said gate polysilicon layer in said area for said NMOS gate and into said area for said body region.
17. The process of claim 5, further including steps:
forming a p-type pre gate etch implant mask over said substrate, after said step of forming said gate polysilicon layer and prior to said step of etching said gate polysilicon layer, which:
exposes an area for said PMOS gate;
exposes an area for said body region of said resistor layer; and
covers an area for said NMOS gate; and
performing a p-type pre gate etch implant operation which implants p-type dopants into said gate polysilicon layer in said area for said PMOS gate and into said area for said body region.
18. The process of claim 5, further including steps:
forming an other component implant mask over said substrate, which:
exposes an area for an other component in said integrated circuit;
cover an area for said PMOS gate;
cover an area for said body region of said resistor layer; and
covers an area for said NMOS gate; and
performing an other component implant operation which implants dopants into said area for said other component.
19. The process of claim 5, in which:
said body region of said resistor layer is p-type; and
said head regions of said resistor layer are p-type.
20. The process of claim 5, in which an average density of p-type dopants in said head regions of said resistor layer is at least 10 percent greater than an average density of p-type dopants in said body region of said resistor layer.