1460709876-94f6c3a4-5ef5-4ba7-ab47-69363b7fb11a

1. A magnetic recording and reproduction apparatus for recording information to, andor reproducing information from, a magnetic tape accommodated in a cassette, the magnetic recording and reproduction apparatus comprising:
a main chassis on which a rotatable head cylinder for recording information to, andor reproducing information from, the magnetic tape is mounted;
a sub chassis on which the cassette is mountable, the sub chassis being movable relative to the main chassis; and
a first guide section for guiding the sub chassis to move relative to the main chassis;
wherein:
the first guide section includes:
a first guide groove provided in one of the main chassis and the sub chassis, the first guide groove extending in a direction in which the sub chassis is movable relative to the main chassis; and
a first projection provided on the other of the main chassis and the sub chassis, the first projection being engageable with the first guide groove and movable along the first guide groove; and

the first guide groove has two opposing sidewalls and two ends between which the first projection is movable, the first projection is contactable with at least one of the two ends at two points on said opposing sidewalls oppsite to each other with respect to a line which is drawn by a center of gravity of the first projection by the movement of the first projection along the first guide groove and the at least one end is formed such that the movement of the first projection toward the at least one end is stopped by the contact with the two points, and the two points have a distance therebetween which is shorter than a width of the first guide groove in a direction perpendicular to the direction in which the sub chassis is movable.
2. A magnetic recording and reproduction apparatus according to claim 1, further comprising:
a second guide section for guiding the sub chassis to move relative to the main chassis;
a third guide section for guiding the sub chassis to move relative to the main chassis;
wherein:
the second guide section includes:
a second guide groove provided in one of the main chassis and the sub chassis, the second guide groove extending in the direction in which the sub chassis is movable relative to the main chassis; and
a second projection provided on the other of the main chassis and the sub chassis, the second projection being engageable with the second guide groove and movable along the second guide groove; and

the third guide section includes:
a third guide groove provided in one of the main chassis and the sub chassis, the third guide groove extending in the direction in which the sub chassis is movable relative to the main chassis; and
a third projection provided on the other of the main chassis and the sub chassis, the third projection being engageable with the third guide groove and movable along the third guide groove;

the main chassis includes a bottom section, a first side section vertical to the bottom section, and a second side section vertical to the bottom section and facing the first side section;
the sub chassis includes a bottom section, a first side section vertical to the bottom section, and a second side section vertical to the bottom section and facing the first side section;
the first guide section is provided on the first side sections of the main chassis and the sub chassis;
the second guide section and the third guide section are each provided on the second side sections of the main chassis and the sub chassis; and
the second guide groove has two ends between which the second projection is movable, the second projection is contactable with at least one of the two ends at two points and the at least one end is formed such that the movement of the second projection toward the at least one end is stopped by the contact with the two points, and the two points have a distance therebetween which is shorter than a width of the second guide groove in a direction perpendicular to the direction in which the sub chassis is movable.
3. A magnetic recording and reproduction apparatus according to claim 2, further comprising:
a fourth guide section for guiding the sub chassis to move relative to the main chassis; and
a fifth guide section for guiding the sub chassis to move relative to the main chassis;
wherein:
the fourth guide section includes:
a fourth guide groove provided in one of the main chassis and the sub chassis, the fourth guide groove extending in the direction in which the sub chassis is movable relative to the main chassis; and
a fourth projection provided on the other of the main chassis and the sub chassis, the fourth projection being engageable with the fourth guide groove and movable along the fourth guide groove; and

the fifth guide section includes:
a fifth guide groove provided in one of the main chassis and the sub chassis, the fifth guide groove extending in the direction in which the sub chassis is movable relative to the main chassis; and
a fifth projection provided on the other of the main chassis and the sub chassis, the fifth projection being engageable with the fifth guide groove and movable along the fifth guide groove; and

the fourth guide section and the fifth guide section are each provided on the bottom sections of the main chassis and the sub chassis.
4. A magnetic recording and reproduction apparatus according to claim 1, wherein at least one of the two ends of the first guide groove is V-shaped.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor memory device comprising:
a plurality of memory blocks each having a plurality of memory cells arranged in rows and columns;
a plurality of sense amplifier bands arranged in correspondence to said plurality of memory blocks so as to be shared between adjacent memory blocks, each sense amplifier band including a plurality of sense amplifiers each sensing and amplifying data in a memory cell in a corresponding memory block when activated;
a plurality of bit line isolation circuits, arranged in correspondence to said plurality of sense amplifier bands, for electrically connecting, when made conductive, corresponding sense amplifier bands to corresponding memory blocks; and
a bit line isolation control circuit for setting at least the bit line isolation circuit provided for a specific memory block to be nonconductive in a standby mode of operation, said specific memory block invariantly being designated.
2. The semiconductor memory device according to claim 1, wherein
said bit line isolation control circuit maintains said plurality of bit line isolation circuits to be nonconductive in said standby mode of operation, to isolate said plurality of memory blocks from the corresponding sense amplifier bands.
3. The semiconductor memory device according to claim 1, wherein
said bit line isolation control circuit includes a program circuit generating a signal for specifying said specific memory block, and the memory blocks other than said specific memory block are electrically connected to the corresponding sense amplifier bands through the corresponding bit line isolation circuits in said standby mode of operation.
4. The semiconductor memory device according to claim 1, wherein
said semiconductor memory device has a normal operation mode for making data access and a data holding mode for holding data stored in the memory cells, and
said bit line isolation control circuit sets said plurality of bit line isolation circuits to be nonconductive at a standby state during activation of a refresh mode instruction signal designating said data holding mode.
5. The semiconductor memory device according to claim 4, wherein
said bit line isolation control circuit controls the bit line isolation circuits so as to electrically connect said plurality of memory blocks to the corresponding sense amplifier bands at said standby state when said refresh mode instruction signal designating said data holding mode is deactivated.
6. The semiconductor memory device according to claim 1, wherein
said bit line isolation control circuit includes
a plurality of bit line isolation select control circuits, arranged in correspondence to said bit line isolation circuits, each for selecting one of a first bit line isolation control signal generated on the basis of a first memory block select signal specifying the memory block arranged for a corresponding bit line isolation circuit and a second bit line isolation control signal generated on the basis of a second memory block select signal specifying the memory block sharing the corresponding sense amplifier band in accordance with a mode selection signal, to apply a selected one to the corresponding bit line isolation circuit as a isolation control signal, said first bit line isolation control signal and said second bit line isolation control signal being opposite in logic to each other.
7. The semiconductor memory device according to claim 6, wherein
each of said bit line isolation control circuits selects said second bit line isolation control signal in accordance with said mode selection signal in a data holding mode for holding data of the memory cells, said second isolation control signal being equal in logic level to said isolation control signal when selected.
8. The semiconductor memory device according to claim 6, wherein
said mode selection signal is an operation mode designation signal designating a data holding mode.
9. The semiconductor memory device according to claim 6, wherein
said mode selection signal is a combined signal of an isolation select activation signal set for each memory block and a mode instruction signal designating a data holding mode, and is programmed for each of said plurality of memory blocks.
10. The semiconductor memory device according to claim 6, wherein
said mode selection signal is generated for each memory block by a program circuit arranged for each of said plurality of memory blocks.
11. The semiconductor memory device according to claim 1, wherein each memory block includes a plurality of word lines arranged corresponding to the rows of the memory cells and connecting to the memory cells on corresponding rows, each word line being kept at a negative potential when nonselected.