1. An integrated circuit, comprising:
an array of non-volatile memory cells, each memory cell of the array having a charge storage region and a plurality of terminals comprising a control gate, a drain, and a source; and
a discharge rate control circuit for controlling a discharge rate of the control gate, the drain, and the source of an erased memory cell, the discharge rate control circuit comprising:
a reference current generator for providing a reference current; and
a first current mirror, coupled to the reference current generator, for providing a first predetermined discharge current for discharging the control gate, the drain, and the source after the erase operation.
2. The integrated circuit of claim 1, wherein the discharge rate control circuit provides a discharge rate determined to reduce voltage overshoot due to capacitive coupling between one or more of the plurality of terminals.
3. Tho integrated circuit of claim 2, wherein the plurality of terminals further comprises a a well terminal.
4. The integrated circuit of claim 1, wherein the discharge rate includes a first discharge rate for a first predetermined time period and a second discharge rate for a second predetermined time period, wherein the second discharge rate is higher than the first discharge rate.
5. The integrated circuit of claim 3, wherein the well terminal is discharged at a first rate for a first predetermined time period and discharged at a second rate for a second predetermined time period, wherein the second rate is higher than the first rate.
6. The integrated circuit of claim 1, further comprising a second current mirror, coupled to the reference current generator, for providing a second predetermined discharge current for discharging a a well terminal of each memory cell of the array after the erase operation.
7. The integrated circuit of claim 6, wherein the second current mirror comprises:
a first transistor having a first current electrode and a control electrode both coupled to the reference current generator, and a second current electrode coupled to a first supply voltage terminal;
a second transistor having a first current electrode capable of being selectively coupled to the well terminal of each of the array of memory cells, a control electrode coupled to the reference current generator, and a second current electrode coupled to the first supply voltage terminal.
8. The integrated circuit of claim 1, wherein the first current mirror comprises:
a first transistor having a first current electrode and a control electrode both coupled to the reference current generator, and a second current electrode selectively coupled to the source and drain of each memory cell of the array of memory cells; and
a second transistor having a having a first current electrode coupled to a source of each memory cell of the array of memory cells, a control electrode coupled to the reference current generator, and a second current electrode selectively coupled to the control gate of each memory cell of the array of memory cells.
9. The integrated circuit of claim 1, further comprising a second current mirror, the second current mirror having an input for receiving a second predetermined discharge current, the second current mirror providing a discharge path from a well terminal of each memory cell of the array, for recycling charge from the the well terminal to a supply voltage terminal.
10. The integrated circuit of claim 6, wherein the discharge rate control circuit further comprises a second reference current generator coupled to the first and second current mirrors.
11. The integrated circuit of claim 1, wherein the drain of each of the memory cells of the array is coupled to a corresponding bit line and all of the sources of the array are coupled together.
12. The integrated circuit of claim 1, wherein the charge storage region is a floating gate of a flash memory cell.
13. An integrated circuit, comprising:
an array of non-volatile memory cells, each memory cell of the array having a control gate, a source, a drain, and a well terminal;
a reference current generator for providing a reference current;
a first current mirror, coupled to the reference current generator, for providing a first predetermined discharge current for discharging the control gate of each memory cell of the array of non-volatile memory cells after an erase operation of the array; and
a second current mirror, coupled to the reference current generator, for providing a second predetermined discharge current for discharging the well terminal of each memory cell of the array of non-volatile memory cells after the erase operation of the array.
14. The integrated circuit of claim 13, wherein the array is erased by applying a positive voltage to the well terminal of each memory cell while applying a negative voltage to the control gate of each memory cell.
15. The integrated circuit of claim 13, wherein the array comprises a plurality of flash memory cells.
16. The integrated circuit of claim 13, wherein the control gate, the drain, the source and the well terminal are all discharged at a rate whereby a discharge voltage overshoot, caused by capacitive coupling between one or more memory cell terminals, is minimized.
17. The integrated circuit of claim 13, wherein the control gate is discharged at a first rate for a first predetermined time period and discharged at a second rate for a second predetermined time period, wherein the second rate is higher than the first rate.
18. The integrated circuit of claim 13, wherein the control gate and the well terminal are both discharged at a first rate for a first predetermined time period and discharged at a second rate for a second predetermined time period, wherein the second rate is higher than the first rate.
19. The integrated circuit of claim 13, wherein each of the memory cells further comprises a deep well terminal coupled to the second current mirror, wherein the deep well terminal is discharged by second discharge current after the erase operation.
20. An integrated circuit comprising:
an array of non-volatile memory cells, each memory cell of the array having a control gate, a source, a drain, a first well terminal, and a second well terminal; and
a discharge rate control circuit for controlling discharging of erase voltages from the control gate, the source, the drain, the first well terminal and the second well terminal of an erased memory cell after an erase operation of the array of non-volatile memory cells.
21. The integrated circuit of claim 20, wherein the discharge rate control circuit comprises:
a reference current generator for providing a reference current; and
a plurality of current mirrors for providing a plurality of discharge currents in response to the reference current, the plurality of current mirrors for discharging the erase voltages at a plurality of predetermined rates.
22. The integrated circuit of claim 20, wherein a discharge rate of the erase voltages is determined to reduce voltage overshoot due to capacitive coupling between one or more of the control gate, the source, the drain, the first well terminal and the second well terminal.
23. The integrated circuit of claim 20, wherein the array of non-volatile memory cells comprises an array of flash memory cells.
24. The integrated circuit of claim 20, wherein the control gate is discharged at a first rate for a first predetermined time period and discharged at a second rate for a second predetermined time period, wherein the second rate is higher than the first rate.
25. The integrated circuit of claim 20, wherein the control gate and the first well terminal are both discharged at a first rate for a first predetermined time period and discharged at a second rate for a second predetermined time period, wherein the second rate is higher than the first rate.
26. A method for controlling a discharge rate of an erase voltage applied to a non-volatile memory cell, the non-volatile memory cell having a plurality of terminals, the method comprising:
providing a reference current;
mirroring the reference current to provide a first mirrored current for discharging a first terminal of the plurality of terminals at a first discharge rate for a first predetermined time; and
mirroring the reference current to provide a second mirrored current for discharging a second terminal of the plurality of terminals at a second discharge rate for a second predetermined time.
27. The method of claim 26, wherein the plurality of terminals comprises a control gate, a floating gate, a source, a drain, and a well region, the well region being in a semiconductor substrate.
28. The method of claim 26, wherein the first discharge rate is approximately equal to the second discharge rate and the first predetermined time is approximately equal to the second predetermined time.
29. The method of claim 26, further comprising:
discharging the first terminal at a third discharge rate for a third predetermined time; and
discharging the second terminal at a fourth discharge rate for a fourth predetermined time.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of generating an optimal path in a domain, comprising:
estimating a traffic volume of said domain;
constructing a traffic matrix in accordance with said estimated traffic volume;
computing a provisioning route for each non-zero element of said traffic matrix, wherein said method is performed for at least one class in descending order of priority, and said provisioning route is open to alteration, said computing including listing and sorting all quadruplets for said at least one class, wherein each of said quadruplets comprises a path having a source, a destination, a rate between said source and said destination, and an indicator of path alterability; and
readjusting said traffic matrix in response to said computed provisioning route, wherein said method is for executing service level agreements (SLAs) and provisioning for traffic flows in networks.
2. The method of claim 1, wherein said domain comprises one of an IP backbone network and a network having a plurality of core nodes connected via logical links to gateway nodes of neighboring domains and at least one bypass node connected to at least one of said core nodes.
3. The method of claim 1, further comprising evaluating cost benefits of reversing a path of at least one previously provisioned flow.
4. The method of claim 1, further comprising maximizing a traffic acceptance rate, and minimizing a hop-bandwidth product.
5. The method of claim 1, said computing step comprising:
selecting a first quadruplet that has not been rejected; and
computing an optimal path between said source and said destination on a subnetwork that comprises all paths meeting bandwidth availability requirements for said first quadruplet, said computing step comprising one of (i) accepting a shortest available path for said first quadruplet if a sub-optimality cost of said first quadruplet equals zero, and (ii) performing a backtracking step to determine if an ideal shortest path of said first quadruplet is feasible if said sub-optimality cost of said first quadruplet is greater than zero.
6. The method of claim 5, said computing step further comprising:
calculating said ideal shortest path and a number of hops in said ideal shortest path H for said first quadruplet;
calculating said shortest available path and a number of hops in said shortest available path H* for said first quadruplet; and
calculating said sub-optimality cost in accordance with the rate, said H and said H*.
7. The method of claim 5, said backtracking step comprising:
creating a matrix that comprises a previous quadruplet configured for alteration and having all links between said source and said destination of said previous quadruplet in said subnetwork;
one of (i) accepting said available shortest path of said first quadruplet if said matrix is empty, (ii) calculating a minimum value of a shifling cost of said previous quadruplet in accordance with said rate of said previous quadruplet in said subnetwork and a difference between a number of hops in said current path and said altered path for said previous quadruplet in said matrix and if said matrix is not empty, and (iii) accepting said available shortest path if said minimum shifting cost of said previous quadruplet exceeds said sub-optimality cost of said first quadruplet, wherein said altered path for said previous quadruplet is generated by deleting said previous quadruplet and adding said first quadruplet; and
if said minimum shifling cost for said first quadruplet exceeds said sub-optimality cost for said previous quadruplet, (i) routing said previous quadruplet on a new path and resetting said available shortest path for said previous quadruplet to said new path, (ii) routing said first quadruplet on said shortest ideal path for said first quadruplet and (iii) resetting said available shortest part to said shortest ideal path for said first quadruplet, and configuring said first quadruplet to not be altered.
8. The method of claim 5, further comprising
selecting a highest non-selected class from a plurality of differentiated service classes; and
adjusting bandwidth availability of said network in accordance with said optimal path of said first quadruplet.
9. The method of claim 1, wherein said readjusting step comprises adjusting one of bandwidth availability wherein said domain comprises a Diffserv network, and optical wavelengths where said domain comprises an optical network.
10. A method of calculating an optimal path of a network, comprising:
selecting a highest non-selected class from a plurality of differentiated service classes;
listing all quadruplets for said selected class, wherein each of said quadruplets comprises a path having a source, a destination, a rate between said source and said destination, and an indicator of path alterability, wherein said quadruplets are sorted according to said rate;
selecting a first quadruplet that has not been rejected;
computing an optimal path between said source and said destination on a subnetwork of said network that comprises all paths meeting bandwidth availability requirements for said first quadruplet, said computing step comprising,
calculating an ideal shortest path and a number of hops in said ideal shortest path H for said first quadruplet,
calculating a shortest available path and a number of hops in said shortest available path H* for said first quadruplet,
calculating a sub-optimality cost in accordance with the rate, said H and said H*, and
one of accepting said shortest available path for said first quadruplet if said sub-optimality cost of said first quadruplet equals zero, and performing backtracking to determine if said ideal shortest path of said first quadruplet is feasible if said sub-optimality cost of said first quadruplet is greater than zero, said backtracking step comprising,
creating a matrix that comprises a previous quadruplet configured for alteration and having all links between said source and said destination of said previous quadruplet in said subnetwork;
one of (i) accepting said available shortest path of said first quadruplet if said matrix is empty, (ii) calculating a minimum value of a shifling cost of said previous quadruplet in accordance with said rate of said previous quadruplet in said subnetwork and a difference between a number of hops in said current path and said altered path for said previous quadruplet in said matrix and if said matrix is not empty, and (iii) accepting said available shortest path if said minimum shifting cost of said previous quadruplet exceeds said sub-optimality cost of said first quadruplet, wherein said altered path for said previous quadruplet is generated by deleting said previous quadruplet and adding said first quadruplet, and
if said minimum shifling cost for said first quadruplet exceeds said sub-optimality cost for said previous quadruplet, routing said previous quadruplet on a new path P* and resefting said available shortest path for said previous quadruplet to said new path P*, routing said first quadruplet on said shortest ideal path for said first quadruplet and resetting said available shortest part to said shortest ideal path for said first quadruplet, and configuring said first quadruplet to not be altered; and
adjusting bandwidth availability of said network in accordance with said optimal path of said first quadruplet.