1. A method of making a free-standing ductile composite comprising:
providing a substrate;
releasably bonding one or more piezoelectric elements to the substrate;
kerfing, while the one or more piezoelectric elements are releasably bonded to the substrate, the piezoelectric elements in a predetermined pattern to form a kerfed pattern;
filling the kerfed pattern with a polymer selected from the group consisting of polyimide and silicone and having a Young’s modulus less than about 20,000 psi at about 120\xb0 C. to form a polymer-piezoelectric composite;
lapping the polymer-piezoelectric composite;
releasing the polymer-piezoelectric composite from the substrate; and
forming a plurality of ink port holes through the polymer.
2. The method of claim 1 wherein the substrate comprises one or more of ceramics, semiconductors, and metals.
3. The method of claim 1 wherein the step of releasably bonding one or more piezoelectric elements to the substrate comprises using one or more of double sided tape, heat releasable polymers, hot melt adhesives, UV releasable tape, chemical soluble polymers, and water soluble polymers to bond one or more piezoelectric elements to the substrate.
4. The method of claim 1, wherein the polymer comprises one or more additives and fillers.
5. The method of claim 1 further comprising curing the polymer before the step of releasing the polymer-piezoelectric composite from the substrate.
6. The method of claim 1 further comprising lapping one or more sides of the polymer-piezoelectric composite to a desired thickness in the range of approximately 10 \u03bcm to approximately 100 \u03bcm.
7. The method of claim 1 further comprising coating a metal to form one or more metal electrodes on at least one side of the polymer-piezoelectric composite.
8. The method of claim 1, further comprising:
filling the kerfed pattern with the polymer while the one or more piezoelectric elements are releasably bonded to the substrate;
curing the polymer while the one or more piezoelectric elements are releasably bonded to the substrate; and
forming an ink port hole between each of the plurality of piezoelectric elements during the formation of the plurality of ink port holes.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor process, comprising:
forming a stacked structure on a substrate;
covering a contact etch stop layer on the stacked structure and the substrate;
forming a material layer on the substrate and exposing a top part of the contact etch stop layer covering the stacked structure, wherein the top part protrudes from the material layer; and
redressing the top part after the material layer is formed.
2. The semiconductor process according to claim 1, wherein the stacked structure comprises a gate and a cap layer from bottom to top.
3. The semiconductor process according to claim 2, wherein the top part is redressed until a part of the cap layer is exposed.
4. The semiconductor process according to claim 2, wherein the cap layer comprises a dual layer.
5. The semiconductor process according to claim 4, wherein the cap layer comprises a nitride layer and an oxide layer from bottom to top.
6. The semiconductor process according to claim 5, wherein the top part is redressed until part of the oxide layer is exposed without exposing the nitride layer.
7. The semiconductor process according to claim 1, wherein the step of forming the material layer on the substrate and exposing the top part of the contact etch stop layer covering the stacked structure comprises:
entirely covering a material on the contact etch stop layer; and
etching back the material to form the material layer.
8. The semiconductor process according to claim 1, wherein the material layer comprises a photoresist layer or an oxide layer.
9. The semiconductor process according to claim 8, further comprising:
removing the photoresist layer after the top part is redressed.
10. The semiconductor process according to claim 2, further comprising:
forming a planarized interdielectric layer on the substrate but exposing the stacked structure after the top part is redressed.
11. The semiconductor process according to claim 10, wherein the step of forming the planarized interdielectric layer comprises:
forming an interdielectric layer to cover the substrate and the stacked structure; and
planarizing the interdielectric layer until the stacked structure is exposed.
12. The semiconductor process according to claim 11, wherein the interdielectric layer is planarized until the cap layer is removed and the gate is exposed.
13. The semiconductor process according to claim 11, wherein the cap layer comprises a nitride layer and an oxide layer from bottom to top, and the interdielectric layer is planarized until the oxide layer is removed and the nitride layer is exposed.
14. The semiconductor process according to claim 13, further comprising:
performing an etching process to remove the nitride layer after the oxide layer is removed.
15. The semiconductor process according to claim 10, further comprising:
removing the gate after the planarized interdielectric layer is formed.
16. The semiconductor process according to claim 2, further comprising:
replacing the gate by a metal gate after the top part is redressed.
17. The semiconductor process according to claim 1, further comprising:
forming a first spacer on the substrate beside the stacked structure after the stacked structure is formed.
18. The semiconductor process according to claim 1, further comprising:
forming a metal silicide on the substrate beside the stacked structure before the contact etch stop layer is covered.
19. The semiconductor process according to claim 1, further comprising:
forming a second spacer on the substrate beside the stacked structure before the contact etch stop layer is covered;
forming a sourcedrain in the substrate beside the second spacer; and
removing at least a part of the second spacer.