1. A method for increasing the data integrity of a non-volatile solid-state memory-based storage device comprising one or more non-volatile memory devices, the method comprising:
receiving data from a host system;
writing a first copy of the data to a first address in the memory devices of the storage device;
checking a bit error rate of the first copy of the data written to the memory devices using an error checking and correction (ECC) implementation; and
writing a second copy of the data to a second address in the memory devices if the bit error rate of the first copy exceeds a threshold, the threshold being lower than or equal to an uncorrectable bit error rate threshold of the data associated with the ECC implementation.
2. The method of claim 1, wherein the memory devices are chosen from the group comprising NAND flash, NOR flash, phase change memory, magnetoresistive memory, and resistive memory.
3. The method of claim 1 wherein, if the bit error rate of the first copy and a bit error rate of the second copy are above the threshold, the data are written to a third location in the memory devices.
4. The method of claims 1, wherein the threshold is one-half of a maximum correctable bit error rate of the data using the ECC implementation.
5. The method of claim 1, wherein the threshold is biased by patterns of errors in the first and second copies of the data.
6. A method for increasing the data integrity of a non-volatile solid-state memory-based storage device comprising one or more non-volatile memory devices, the method comprising:
receiving data from a host system;
encoding the data with the storage device for error checking and correction using an error checking and correction (ECC) implementation;
writing a first copy of the data to a first address in the memory devices;
checking a bit error rate of the first copy of the data written to the memory devices; and
writing a second copy of the data to a second address in the memory devices if the bit error rate of the first copy exceeds a threshold, the threshold not exceeding an uncorrectable bit error rate threshold of the data associated with the ECC implementation.
7. The method of claim 6, wherein the non-volatile solid-state memory devices are chosen from the group comprising NAND flash, NOR flash, phase change memory, magnetoresistive memory, and resistive memory.
8. The method of claim 6 wherein, if the bit error rate of the first copy and a bit error rate of the second copy are above the threshold, the data are written to a third location in the memory devices.
9. The method of claims 6, wherein the threshold of the bit error rate is one-half of a maximum correctable bit error rate of the data using the ECC implementation.
10. The method of claim 8, wherein the threshold is biased by patterns of errors in the first and second copies of the data.
11. A method for increasing the data integrity of a non-volatile solid-state memory-based storage device comprising one or more non-volatile memory devices, the method comprising:
receiving data from a host system;
encoding the data with the storage device for error checking and correction using an error checking and correction (ECC) implementation;
writing a first copy and a second copy of the data to a first address and a second address, respectively, in the memory devices;
checking the bit error rates of the first and second copies of the data written to the memory devices; and
discarding either of the first and second copies having a higher bit error rate.
12. The method of claim 11, further comprising:
logging of bit error rates of blocks of the memory devices;
calculating an average bit error rate for each block; and
if the average bit error rate of a block exceeds a threshold, erasing the block and suspending the block from use by the storage device until the average wear count of all blocks has increased an incremental number of cycles.
13. The method of claim 12 where the incremental number of cycles of the average wear count is a percentage of programerase cycles logged for the block.
14. The method of claim 11, wherein the memory devices are chosen from the group comprising NAND flash, NOR flash, phase change memory, magnetoresistive memory, and resistive memory.
15. A mass storage device comprising a host system interface and a printed circuit board having a controller and one or more solid-state non-volatile memory devices mounted thereon, the memory devices being addressable individually over discrete channels of the controller, the controller comprising:
an error checking and correction (ECC) engine operable to encode data written from a host system to the storage device according to an ECC algorithm and to determine bit error rates of data written to the memory devices;
means for writing a set of the data to a first address of the memory devices and, if the bit error rate of the set of data is within a range acceptable for error correction but exceeds a threshold, writing a copy of the set of the data to a second address of the memory devices; and
means for comparing the bit error rate of the copy of the set of the data written to the second address to the bit error rate of the set of the data written to the first address and discarding the set of the data or the copy thereof having a higher bit error rate.
16. The mass storage device of claim 15, wherein the memory devices are chosen from the group comprising NAND flash, NOR flash, phase change memory, magnetoresistive memory, and resistive memory.
17. A solid-state mass storage device comprising a controller, a cache memory, and one or more non-volatile memory devices, the memory devices each being connected to an independent channel of the controller, the controller comprising:
an error checking and correction (ECC) engine for ECC-encoding data written from a host system to the storage device before writing the ECC-encoded data to one of the memory devices;
means for monitoring a bit error rate of the ECC-encoded data written to the memory devices;
means for writing a first copy of the ECC-encoded data to a first address of the memory devices and, in parallel, writing a second copy of the ECC-encoded data to a second address of the memory devices; and
means for monitoring the bit error rates of the first and second copies of the ECC-encoded data and discarding either of the first and second copies having a higher bit error rate.
18. The method of claim 17, wherein the memory devices are chosen from the group comprising NAND flash, NOR flash, phase change memory, magnetoresistive memory, and resistive memory.
19. A solid-state mass storage device comprising a controller, a cache memory, and one or more non-volatile memory devices, the memory devices each being connected to an independent channel of the controller, the controller comprising:
an error checking and correction (ECC) engine for ECC-encoding data written from a host system to the storage device before writing the ECC-encoded data to the memory devices;
means for monitoring a bit error rate of the ECC-encoded data written to the memory devices and, if an average of the bit error rate of the ECC-encoded data increases beyond a threshold, switching to a parallel mode by writing a first copy of the ECC-encoded data to a first address of the memory devices and substantially simultaneously writing a second copy of the ECC-encoded data to a second address of the memory devices; and
means for monitoring the bit error rates of the first and second copies of the ECC-encoded data and discarding either of the first and second copies having a higher bit error rate.
20. The method of claim 19, wherein the non-volatile solid-state memory devices are chosen from the group comprising NAND flash, NOR flash, phase change memory, magnetoresistive memory, and resistive memory.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A multi-speed automatic transmission adapted for a motor vehicle comprising:
a transmission case;
an input shaft having a first input drive gear and a second input drive gear;
a first output shaft having a first output drive gear at an one end portion thereof and arranged in parallel with the input shaft;
a second output shaft having a second output drive gear and arranged in parallel with the input shaft and the first output shaft;
a first input driven gear rotatable on the first output shaft and engaging with the first input drive gear;
a second input driven gear rotatable on the second output shaft and engaging with the second input dive gear;
an output driven gear in mesh with the first output drive gear and the second output drive gear;
a first planetary gear set interposed between the input shaft and the first output drive gear and arranged in coaxial with the first output shaft to change a rotational speed of the input shaft to a rotational speed of the first output drive gear, the first planetary gear set including a first sun gear, a first ring gear, a plurality of first pinions supported by a first pinion carrier and engaging with the first sun gear and the first ring gear;
a second planetary gear set interposed between the input shaft and the second output drive gear and arranged in coaxial with the second output shaft to change the rotational speed of the input shaft to a rotational speed of the second output drive gear, the second planetary gear set including a second sun gear, a second ring gear, a plurality of second pinions supported by a second pinion carrier and engaging with the second sun gear and the second ring gear; and
an intermediate gear arranged in coaxial with the input shaft and connecting with the first sun gear and the second sun gear, wherein
the input shaft is connectable with the first ring gear through the first input drive gear and the first input driven gear and is connectable with the second pinion carrier through the second input drive gear and the second input driven gear,
the first output shaft being connectable with the first pinion carrier,
the second output shaft being connectable with the second ring gear,
the second pinion carrier being fixable to the transmission case,
the first sun gear and the second sun gear being connectable with the input shaft through the first input drive gear and the first input driven gear and through the intermediate gear, and the first sun gear and the second sun gear being fixable to the transmission case.
2. The multi-speed automatic transmission according to claim 1, further comprising:
an intermediate member which is arranged in coaxial with the first output shaft and is arranged between the input shaft and the first ring gear and between the input shaft and the first sun gear so that the intermediate member can be connected with the first ring gear with by a first clutch and can be connected with the first sun gear by a second clutch, wherein
the input shaft and the intermediate member are connectable with each other by a moving-off clutch.
3. The multi-speed automatic transmission according to claim 2, further comprising:
the moving-off clutch is arranged on one of the input shaft and the intermediate member.
4. The multi-speed automatic transmission according to claim 3, further comprising:
a first reaction gear engaged with the intermediate gear and connected with the first sun gear, and
a second reaction gear engaged with the intermediate gear and connected with the second sun gear, wherein
the intermediate gear and the first reaction gear provide an overdrive gear ratio, the intermediate gear and the second reaction gear providing a reduced gear ratio.
5. The multi-speed automatic transmission according to claim 2, further comprising:
a first reaction gear engaged with the intermediate gear and connected with the first sun gear, and
a second reaction gear engaged with the intermediate gear and connected with the second sun gear, wherein
the intermediate gear and the first reaction gear provide an overdrive gear ratio, the intermediate gear and the second reaction gear providing a reduced gear ratio.
6. The multi-speed automatic transmission according to claim 1, further comprising:
a first reaction gear engaged with the intermediate gear and connected with the first sun gear, and
a second reaction gear engaged with the intermediate gear and connected with the second sun gear, wherein
the intermediate gear and the first reaction gear provide an overdrive gear ratio, the intermediate gear and the second reaction gear providing a reduced gear ratio.