1. An integrated hydrocracking process for producing cracked hydrocarbons from a feedstock including:
a. separating the hydrocarbon feed into an aromatic-lean fraction and an aromatic-rich fraction;
b. hydroprocessing the aromatic-rich fraction in a first stage hydroprocessing reaction zone to produce a first stage hydroprocessing reaction zone effluent;
c. fractionating the first stage hydroprocessing reaction zone effluent to produce one or more fractionating zone product streams and one or more fractionating zone bottoms streams;
d. hydroprocessing a mixture of at least a portion of fractionating zone bottoms stream and aromatic-lean fraction in a second stage hydroprocessing reaction zone to produce a second stage hydroprocessing reaction zone effluent; and
e. conveying the second stage hydroprocessing reaction zone effluent to the step of fractionating.
2. The process of claim 1, wherein the first stage hydroprocessing reaction zone is operated under relatively severe conditions effective to remove heteroatoms from, and to hydrocrack, at least a portion of aromatic compounds contained in the aromatic-rich fraction.
3. The process of claim 1, wherein the second stage hydroprocessing reaction zone is operated under relatively mild conditions effective to remove heteroatoms from, and to hydrocrack, at least a portion of paraffin and naphthene compounds contained in the mixture of fractionating zone bottoms stream and aromatic-lean fraction.
4. The process of claim 1, wherein the aromatic-rich fraction includes aromatic nitrogen compounds including pyrrole, quinoline, acridine, carbazole and their derivatives.
5. The process of claim 1, wherein the aromatic-rich fraction includes aromatic sulfur compounds including thiophene, benzothiophenes and their derivatives, and dibenzothiophenes and their derivatives.
6. The process of claim 1, wherein separating the hydrocarbon feed into an aromatic-lean fraction and an aromatic-rich fraction comprises:
subjecting the hydrocarbon feed and an effective quantity of extraction solvent to an extraction zone to produce
an extract containing a major proportion of the aromatic content of the hydrocarbon feed and a portion of the extraction solvent and
a raffinate containing a major proportion of the non-aromatic content of the hydrocarbon feed and a portion of the extraction solvent;
separating at least substantial portion of the extraction solvent from the raffinate and retaining the aromatic-lean fraction; and
separating at least substantial portion of the extraction solvent from the extract and retaining the aromatic-rich fraction.
7. An integrated apparatus for processing heavy hydrocarbon feedstocks to produce clean transportation fuels comprising:
an aromatic separation zone operable to extract aromatic compounds from the hydrocarbon feed, the aromatic separation zone including an inlet for receiving the hydrocarbon feed, an aromatic-rich outlet and an aromatic-lean outlet;
a first stage hydroprocessing reaction zone having an inlet in fluid communication with the aromatic-rich outlet and an outlet for discharging first stage hydroprocessing reaction zone effluent;
a fractionating zone having an inlet in fluid communication with both the first stage hydroprocessing reaction zone effluent and a second stage hydroprocessing reaction zone effluent, one or more outlets for discharging product and one or more outlets for discharging fractionating zone bottoms; and
a second stage hydroprocessing reaction zone having an inlet in fluid communication with both the fractionating zone bottoms stream and the aromatic-lean outlet, and an outlet for discharging second stage hydroprocessing reaction zone effluent.
8. The process of claim 1, wherein the one or more fractionating zone product streams include diesel andor naptha.
9. The process of claim 1, wherein at least a portion of the one or more fractionating zone bottoms streams are recycled back to step (a) andor step (b).
10. The process of claim 1, wherein separating the hydrocarbon feed into an aromatic-lean fraction and an aromatic-rich fraction is carried out in a mixer-settler apparatus.
11. The process of claim 1, wherein separating the hydrocarbon feed into an aromatic-lean fraction and an aromatic-rich fraction is carried out in a centrifugal contactor.
12. The process of claim 1, wherein separating the hydrocarbon feed into an aromatic-lean fraction and an aromatic-rich fraction is carried out in a contacting column.
13. The process of claim 12, wherein the contacting column is a tray column.
14. The process of claim 12, wherein the contacting column is a packed bed column.
15. The process of claim 12, wherein the contacting column is a rotating disc contactor.
16. The process of claim 12, wherein the contacting column is a pulse column.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An amplifier comprising:
a. an amplifier input node;
b. an amplifier output node;
c. a supply terminal;
d. an impedance coupled between the supply terminal and the amplifier output node, the impedance including a calibration port, an enable port, and a control terminal coupled to the input node;
e. impedance calibration circuitry coupled to the calibration port; and
f. update logic coupled between the enable port and at least one of the amplifier input node and the amplifier output node.
2. The amplifier of claim 1, wherein the impedance is coupled in series with a transistor.
3. The amplifier of claim 1, wherein the impedance includes a plurality of transistors of various gate widths.
4. The amplifier of claim 3, wherein the gate widths are binary coded.
5. The amplifier of claim 1, wherein the impedance is a pull-down driver.
6. The amplifier of claim 5, further comprising a second supply terminal and a pull-up impedance coupled between the second supply terminal and the amplifier output node, the pull-up impedance including a second calibration port, a second enable port, and a second control terminal.
7. The amplifier of claim 6, wherein the second control terminal is coupled to the amplifier input node.
8. The amplifier of claim 1, further comprising a sequential storage element coupled between the amplifier input node and the update logic.
9. The amplifier of claim 1, wherein the impedance calibration circuitry includes a variable impedance having a third calibration port, the variable impedance exhibiting a first range of impedances proportional to a second range of impedances exhibited by the impedance.
10. The amplifier of claim 1, wherein the impedance is one of a plurality of impedances coupled between the supply terminal and the amplifier output node.
11. A method of driving a signal over a channel, the method comprising:
a. monitoring the signal for first and second logic levels;
b. pulling, in response to the first logic level, the channel toward a supply voltage at a first drive strength;
c. adjusting, in response to the second logic level, the first drive strength to a second drive strength; and
d. pulling, in response to the first logic level, the channel toward the supply voltage at the second drive strength.
12. The method of claim 11, further comprising:
a. pulling, in response to the second logic level, the communication channel toward a second supply voltage at a third drive strength;
b. adjusting, in response to the first logic level, the third drive strength to a fourth drive strength; and
c. pulling, in response to the second logic level, the communication channel toward the second supply voltage at the fourth drive strength.
13. The method of claim 1 1, further comprising adjusting a drive impedance to adjust the first drive strength.
14. A computer-readable medium having stored thereon a data structure defining an amplifier, the data structure comprising:
a. first data representing an input node, an output node, and a supply terminal;
b. second data representing an impedance coupled between the supply terminal and the output node, the second data specifying the impedance as including a calibration port, an enable port, and a control terminal coupled to the input node;
c. impedance calibration circuitry coupled to the calibration port; and
d. update logic coupled between the input node and the enable port.
15. A driver comprising:
a. an input node receiving an input signal, including first and second logic levels;
b. an output node;
c. a supply terminal;
d. a drive element coupled between the supply terminal and the output node, the drive element including a control terminal coupled to the input node, wherein the drive element exhibits a first impedance in an active state responsive to the first logic level and a second impedance in an inactive state responsive to the second logic level, the second impedance having a value higher than the first impedance; and
e. means for adjusting the first impedance when the drive element is in the inactive state.
16. An amplifier comprising:
a. an input node;
b. an output node;
c. a supply terminal;
d. a plurality of drive elements coupled in parallel between the supply terminal and the output node, each of the drive elements including a calibration port, an enable port, and a control terminal coupled to the input node; and
e. an impedance calibration control block coupled to the calibration ports.
17. The amplifier of claim 16, the impedance calibration control block including impedance calibration circuitry selectively coupled to the calibration ports.
18. The amplifier of claim 17, the impedance calibration control block including sequential storage elements coupled between the impedance calibration circuitry and each of the calibration ports.
19. The amplifier of claim 17, further comprising update control circuitry coupled to each of the enable ports.
20. The amplifier of claim 19, wherein the update control circuitry selectively disables at least one of the drive elements, leaving the remaining ones of the drive elements enabled.
21. The amplifier of claim 19, wherein the impedance calibration control block includes an update control port coupled to the update control circuitry, and wherein the update control circuitry selectively couples the impedance calibration circuitry to at least one of the calibration ports.
22. The amplifier of claim 16, wherein the impedance calibration control block successively calibrates each of the drive elements.
23. The amplifier of claim 22, further comprising update control circuitry that disables one of the drive elements while the impedance calibration control block calibrates the disabled one of the drive elements.
24. The amplifier of claim 23, wherein the update control circuitry controls the impedance calibration control block to determine which of the drive elements is calibrated.