1. A backside-illuminated image sensor comprising:
a semiconductor substrate having a first substrate surface and a second substrate surface, the first substrate surface being opposite to the second substrate surface;
one or more light sensing elements in the semiconductor substrate, the light sensing elements being arranged for receiving image light from outside the semiconductor substrate;
a cavity formed in the semiconductor substrate, the cavity having a base surface overlying the light sensing elements, and the cavity extending from the first substrate surface to the base surface; and
at least one first electrical path formed between the first substrate surface and the base surface;
wherein the first electrical path being formed on at least a portion of a sidewall of the cavity and residing on the cavity to facilitate electronic signal communication between the first substrate surface and the base surface;
wherein the first substrate surface being an image sensor backside; and
wherein the image light being allowed to reach the light sensing elements through the base surface such that a distance traveled by the image light, through the semiconductor substrate, towards the image sensor backside and to the light sensing elements is shorter than it is if the cavity is absent.
2. The image sensor of claim 1, wherein the cavity being formed by etching on the semiconductor substrate.
3. The image sensor of claim 1, wherein the cavity having the sidewall comprising oxygen ion implant; wherein the oxygen ion implant serves as stoppers during etching for cavity formation in the semiconductor substrate.
4. The image sensor of claim 1, further comprising a plurality of micro-optical devices on the cavity base surface, wherein each of the micro-optical devices is configured to optically process a portion of the image light and direct the post-optically-processed portion of the image light to one of the light sensing elements.
5. The image sensor of claim 4, wherein each of the micro-optical devices comprises a microlens and a color filter.
6. The image sensor of claim 1, further comprising an anti-reflective film on the cavity.
7. The image sensor of claim 6, wherein the anti-reflective film covering the first electrical paths for avoiding undesired interference, generated from reflected incident light, to the light sensing elements.
8. The image sensor of claim 1, further comprising:
at least one second electrical path electrically connected to the first electrical path;
wherein the second electrical path passes through one or more first vias extending from the base surface to the second substrate surface, thereby allowing electronic signal communication between one or more of first devices on the second substrate surface and one or more of second devices electrically connectable to the first substrate surface.
9. The image sensor of claim 8, further comprising a substantially-transparent cover plate attached to the first substrate surface.
10. The image sensor of claim 8, further comprising a handling substrate attached to the second substrate surface, thereby providing additional mechanical support to the image sensor.
11. The image sensor of claim 8, wherein at least one of the first vias has a substantially uniform cross-sectional area or a substantially non-uniform cross-sectional area.
12. The image sensor of claim 9, wherein the substantially-transparent cover plate being a glass plate.
13. The image sensor of claim 9, wherein the substantially-transparent cover plate further comprising at least one second via, and one or more third devices being attached on the substantially-transparent cover plate such that the third devices are electrically connectable to the first substrate surface through the second via, or to the second substrate surface through the second via, the first electrical path and second electrical path, thereby allowing a higher degree of device integration.
14. The image sensor of claim 1, further comprising a buried insulator to separate the semiconductor substrate into a bulk serving as the sidewall of the cavity and an active region, on which one or more electronic components are fabricated.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A computer readable storage medium including processor executable instructions, the computer readable storage medium comprising:
instructions for storing a thread in a linked list associated with a specific processor of a plurality of processors in a computer system, the linked list accessible to the plurality of processors;
instructions for adding the thread stored in the linked list to a ready list associated with the specific processor, the ready list is only accessible to the specific processor and the threads are stored in the ready list in an order of priority; and
instructions for executing the thread.
2. The computer readable storage medium of claim 1, further comprising:
instructions for determining that the linked list is empty;
instructions for adding the thread to the linked list; and
instructions for sending an interrupt to the specific processor.
3. The computer readable storage medium of claim 1, further comprising:
instructions for determining that the linked list is not empty; and
instructions for adding another thread to the linked list.
4. The computer readable storage medium of claim 1, wherein the instructions for adding the thread stored in the linked list to the ready list further comprises:
instructions for setting a head entry in the linked list to an active state, the active state indicating that the specific processor is accessing the linked list; and
instructions for inserting the thread into to the ready list in order of priority;
instructions for setting the head entry in the linked list to an empty state.
5. The computer readable storage medium of claim 1, further comprising:
instructions for storing an operating system thread in a linked list associated with a virtual machine, the linked list accessible to the plurality of processors;
instructions for adding the operating system thread stored in the linked list to a ready list associated with a specific processor, the ready list is only accessible to the specific processor and operating system threads are stored in the ready list in order of priority; and
instructions for executing the operating system thread.
6. The computer readable storage medium of claim 1, further comprising:
instructions for placing the specific processor into an idle state and configuring the specific processor to monitor the linked list;
instructions for detecting that the thread was written to the linked list; and
instructions for exiting the idle state.
7. The computer readable storage medium of claim 1, wherein the instructions for storing the thread in the linked list further comprise:
instructions for executing an atomic compare and swap operation on the linked list to add the thread to the linked list.
8. A computer system, comprising:
circuitry for determining that a linked list for a processor is empty, the linked list configured to store threads;
circuitry for adding a thread to the linked list and sending an interrupt to the processor;
circuitry for determining that the thread was added to the linked list for the processor in response to receiving the interrupt; and
circuitry for adding the thread to a ready list for the processor, the processor configured to execute threads from the ready list in an order of thread priority, and the ready list is exclusively accessible by the processor.
9. The computer system of claim 8, further comprising:
circuitry for determining that the linked list for the processor is not empty; and
circuitry for adding an additional thread to the linked list.
10. The system of claim 8, wherein the thread is a virtual processor thread.
11. The system of claim 8, wherein the circuitry for adding the thread to the ready list further comprises:
circuitry for setting a head entry in the linked list to an active state, the active state indicating that the processor is accessing the linked list; and
circuitry for inserting the information related to the pending thread into the ready list in order of priority; and
circuitry for setting the head entry in the linked list to an empty state.
12. The system of claim 8, wherein the circuitry for adding the thread to the linked list further comprises:
circuitry for executing an atomic compare and swap operation on the linked list to add the thread to the linked list.
13. The system of claim 11, further comprising:
circuitry for determining that the head entry in the linked list was changed from the active state;
circuitry for identifying an additional thread that was added to the linked list; and
circuitry for inserting the thread into the ready list based on the additional thread’s priority.
14. A method, comprising:
entering, by a processor, an idle state, wherein the processor is configured to monitor a memory address associated with a linked list while in the idle state;
detecting, by the processor, that a thread was added to the linked list and exiting the idle state; and
adding the thread to a ready list for the processor, the processor configured to execute threads from the ready list in an order of priority and the ready list is exclusively accessible by the processor.
15. The method of claim 14, wherein adding the thread to the ready list further comprises:
setting a head entry in the linked list to an active state, the active state indicating that the specific processor is accessing the linked list;
inserting the thread into to the ready list in order of priority; and
setting the head entry in the linked list to an empty state.
16. The method of claim 14, further comprising:
writing, by the processor, information to a shared memory location, the information identifying that the processor is entering the idle state.
17. The method of claim 14, further comprising:
setting, by the processor, a head entry for the linked list to a value that indicates that the linked list is empty.
18. The method of claim 15, wherein setting the head entry in the linked list to the empty state further comprises:
executing an atomic compare and swap operation on the linked list to set the head entry to the empty state.
19. The method of claim 16, further comprising:
determining, by a second processor, that the first processor has entered the idle state from the information in the shared memory location; and
adding, by the second processor, a thread to the linked list, wherein the thread is added to the monitored memory address.
20. The method of claim 17, further comprising:
determining, by a second processor, that the linked list is empty; and
adding an additional thread to the linked list and sending an interrupt to the processor.