I claim:
1. A comparator circuit, comprising:
an input for receiving an input signal;
an output terminal outputting an output signal;
a first comparator connected to said input and receiving the input signal, when the input signal exceeds a threshold value T1, said first comparator generates a first output signal switching from a first logic signal to a second logic signal, in which case a switching of the output signal from the first logic signal to the second logic signal can be initiated only by said first comparator switching from the first logic signal to the second logic signal;
a monitoring circuit connected between said input and said output terminal, said monitoring circuit, including:
a second comparator connected to said input and has a switching hysteresis with a switching-on threshold T2 and a switching-off threshold T3, where T2>T3, said second comparator and said first comparator each have an output;
an output circuit; and
a logic circuit connected to said output circuit, to said output of said first comparator, and to said output of said second comparator, said logic circuit links said output of said first comparator and said second comparator to said output circuit in such a manner that, when the input signal exceeds the threshold value T1, said output circuit emits the second logic signal and then remains inhibited against returning to the first logic signal until the input signal has once again fallen below the threshold value T1 after exceeding the switching-on threshold value T2; and
a reset circuit connected to said output circuit and said logic circuit, said reset circuit able to reset said output circuit to a quiescent state irrespective of a state of said first comparator and said second comparator, and in the quiescent state the output signal at said output terminal is at the first logic signal, and the output circuit maintains its present state until said first comparator and said second comparator output signals being the first logic signal.
2. The comparator circuit according to claim 1, wherein said output circuit is a flip-flop with a set input, a reset input and an output being said output terminal.
3. The comparator circuit according to claim 2, wherein said logic circuit has a first AND gate, a second AND gate, a first NOT gate with an output, and a second NOT gate with an output, said first AND gate having a first input connected to said output of said first comparator and a second input connected to said output of said second NOT gate, said second NOT gate having an input connected to said output of said second comparator, said second AND gate having a first input connected to said output of said first NOT gate and a second input of said second AND gate connected to said output of said second comparator, said first NOT gate having an input connected to said output of said first comparator.
4. The comparator circuit according to claim 3, wherein said flip-flop includes a first NOR gate having an output and inputs and a second NOR gate having an output and inputs, said output of said first NOR gate connected to one of said inputs of said second NOR gate, said output of said second NOR gate connected to one of said inputs of said first NOR gate.
5. The comparator circuit according to claim 4, wherein said reset circuit includes:
a third NOT gate having an input and an output;
an input connection connected to said input of said third NOT gate;
a third AND gate having a first input connected to said output of said second NOR gate of said flip-flop, a second input connected to said output of said third NOT gate, and an output connected to one of said inputs of said first NOR gate of said flip-flop;
a further flip-flop having a set input, a reset input connected to said input connection for receiving a reset signal, and an output connected to a third input of said first AND gate and to a third input of said second AND gate; and
an exclusive-OR gate having an output connected to said set input of said further flip-flop, a first input connected to said output of said first NOT gate and to said second input of said second AND gate, and a second input connected to said output of said third AND gate.
6. The comparator circuit according to claim 1, wherein the threshold value T1, the switch-on threshold T2 and the switch-off threshold T3 are chosen such that T3<T1<T2.
7. The comparator circuit according to claim 1, wherein the first logic signal is low, and the second logic signal is high.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A near-field radar obstacle detection apparatus comprising:
a fixed beam planar radar antenna; and
an adaptation device for shaping a transmitted or received radiation of said antenna, including a plurality of dielectric elements that individually constitute different surface portions of an imaginary idealized quasi-spherical or quasi-cylindrical reflector disposed substantially at a near-field boundary of said antenna.
2. The apparatus of claim 1, wherein said dielectric elements are supported by a radome that is otherwise transparent to the transmitted or received radiation.
3. The apparatus of claim 2, wherein said dielectric elements are insert-molded into said radome.
4. The apparatus of claim 1, wherein two or more of said dielectric elements are combined about a diffraction point of said antenna to form a single multi-faceted dielectric element disposed substantially at said near-field boundary.
5. The apparatus of claim 1, wherein said idealized reflector is quasi-cylindrical, and said dielectric elements are defined by different surface portions of a post disposed substantially at said near-field boundary.
6. The apparatus of claim 1, wherein said adaptation device compensates for off-axis or off-center orientation of said antenna.
7. The apparatus of claim 1, wherein said adaptation device extends a field-of-view of said antenna.
8. The apparatus of claim 1, wherein a radar antenna is mounted on a bumper of said vehicle, and said adaptation device is supported on a fascia that surrounds said bumper.