1 An emergency device for relighting a windmilling turbojet, the jet comprising a fan driven by a low-pressure turbine via a first shaft and a compressor driven by a high-pressure turbine via a second shaft disposed coaxially around the first shaft, said device comprising a differential interconnecting said first and second shafts while compensating for their different speeds of rotation in normal operation or the turbojet, and a braking system connected to the differential so as to enable it to be slowed down or blocked when the turbojet shuts down, thereby enabling the first shaft to entrain the second shaft so that it reaches a speed that favors relighting of the turbojet.
2 A device according to claim 1, wherein the differential comprises at least one planet-carrying annular gear rotating about the first and second shafts and coupled in rotation with a rotary portion of the braking system.
3 A device according to claim 1, wherein the differential acts as a multiplier from the first shaft to the second shaft when it is slowed down or blocked by the braking system.
4 A device according to claim 1, wherein the first and second shafts are co-rotating shafts.
5 A device according to claim 1, wherein the first and second shafts are contra-rotating shafts.
6 A device according to claim 1, wherein the braking system includes at least one disk brake.
7 A device according to claim 1, wherein the braking system includes a retarder.
8 A device according to claim 1, wherein the differential is placed together with the braking system outside an intermediate casing.
9 A device according to claim 1, further comprising an electronic computer enabling the braking system to be controlled and calculating the braking pressure that is required to adapt the transfer of energy from the first shaft to the second shaft.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor integrated circuit device comprising:
a first N-channel MOSFET and first P-channel MOSFET each having a gate insulator film with a first film thickness, and
a second N-channel MOSFET and second P-channel MOSFET each having a gate insulator with a second film thickness less than said first film thickness, a polysilicon layer constituting a gate electrode of said second N-channel MOSFET being doped with an N-type impurity and a polysilicon layer constituting a gate electrode of said second P-channel MOSFET being doped with a P-type impurity,
wherein gate electrodes of said first N-channel MOSFET and said first P-channel MOSFET are formed as one body and connected to each other,
wherein said gate electrodes of said first N-channel MOSFET and said first P-channel MOSFET are doped with a same conductive type impurity.
2. A semiconductor integrated circuit device according to claim 1, wherein said first conductive type impurity is an N-type impurity.
3. A semiconductor integrated circuit device according to claim 2, wherein a gate length of said first N-channel MOSFET and first P-channel MOSFET is formed to be longer than a gate length of said second N-channel MOSFET and second P-channel MOSFET.
4. A semiconductor integrated circuit device according to claim 3, wherein the gate electrode of said second N-channel MOSFET and the gate electrode of said second P-channel MOSFET are connected to each other with a metal layer in an upper layer connected to those gate electrodes.
5. A semiconductor integrated circuit device according to claim 4, wherein a first circuit including said first N-channel MOSFET and first P-channel MOSFET is driven by a first operation voltage,
a second circuit including said second N-channel MOSFET and second P-channel MOSFET is driven by a second operation voltage less than said first operation voltage.
6. A semiconductor integrated circuit device according to claim 5, wherein
said semiconductor integrated circuit device comprises a DRAM and a logic circuit,
said second N-channel MOSFET and said second P-channel MOSFET are used for said logic circuit and for memory peripheral circuits including a sense amplifier of said DRAM,
said first N-channel MOSFET and said first P-channel MOSFET are used for word drivers of said DRAM.
7. A semiconductor integrated circuit device according to claim 1, further comprising:
a third N-channel MOSFET and a third P-channel MOSFET,
wherein gate electrodes of said third N-channel MOSFET and said third P-channel MOSFET are formed as one body and connected to each other,
wherein a polysilicon layer constituting said gate electrodes of said third N-channel MOSFET and said third P-channel MOSFET is doped with a first conductive type impurity, and
wherein gate electrodes of said third N-channel MOSFET and said third P-channel MOSFET are connected to each other with a metal layer in an upper layer connected to those electrodes.
8. A semiconductor integrated circuit device according to claim 1, wherein
said gate electrodes of said first N-channel MOSFET and said first P-channel MOSFET comprise a polysilicon layer.