What is claimed is
1. A state indicating information setting circuit comprising:
a first state holding part for inputting thereto a signal indicating either a predetermined first state or a predetermined second state, holding the state indicated by said signal input and outputting said state;
a second state holding part for inputting thereto the signal output from said first state holding part, holding the state indicated by said signal input and outputting said state;
a first state comparing part inputting thereto a predetermined state detection signal and the signal output from said second state holding part, and outputting a signal indicating said predetermined first state to said first state holding part when the respective states indicated by the respective signals input are different from one another, and outputting a signal indicating said predetermined second state when these states are same as one another;
a second state comparing part comparing the states of the respective signals output from said first state holding part and said second state holding part, and outputting a signal indicating said predetermined second state as a state detection signal clearing signal when the respective states indicated by said input signals are different from one another; and
a third state comparing part comparing the states of the respective signals output from said first state holding part and said second state holding part, outputting a state detection signal indicating said predetermined first state when said states of the respective signals input are different from each other, and outputting the state non-detection signal indicating said predetermined second state when said states are same as one another.
2. A state indicating information setting circuit comprising:
a first state holding part inputting thereto a signal indicating either a predetermined first state or a predetermined second state, holding the state indicated by said signal input, and outputting said state;
a second state holding part inputting thereto the signal output from said first state holding part, and holding and outputting the state indicated by said signal input, and outputting said state;
a third state holding part inputting thereto the signal output from said second state holding part, and holding and outputting the state indicated by said signal input, and outputting said state;
a first state comparing part inputting thereto a predetermined state detection signal and the signal output from said second state holding part, outputting a signal indicating said predetermined first state to said first state holding part when the respective states indicated by the respective signals input are different from one another, and outputting a signal indicating said predetermined second state when these states are same as one another;
a second state comparing part comparing the states of the respective signals output from said first state holding part and said second state holding part, and outputting a signal indicating said predetermined second state as a state detection signal clearing signal when the respective states indicated by said input signals are different from one another; and
a third state comparing part comparing the states of the respective signals output from said first state holding part and said third state holding part, outputting a state detection signal indicating said predetermined first state when said states of the respective signals input are different from each other, and outputting the state non-detection signal indicating said predetermined second state when said states given are same as one another.
3. A state indicating information setting circuit comprising:
a first state holding part holding a state of an input signal, and outputting a signal indicating said state thus held;
a second state holding part holding the state of the signal output from said first state holding part, and outputting a signal indicating said state thus held;
a state inverting part responsive to a predetermined state detection signal for outputting to said first state holding part a signal indicating a state which is different from the state indicated by the signal output from said second state holding part;
a state detection signal outputting part comparing the states of the respective signals output from said first state holding part and said second state holding part, outputting the state detection signal when said states are different from one another, and outputting a state non-detection signal when said states are same as one another; and
a state detection signal clearing part comparing the states of the respective signals output from said first state holding part and said second state holding part, and outputting a state detection signal clearing signal when said states are different from one another.
4. A state indicating information setting circuit comprising:
a first state holding part holding a state of an input signal, and outputting a signal indicating said state thus held;
a second state holding part holding the state of the signal output from said first state holding part, and outputting a signal indicating said state thus held;
a third state holding part holding the state of the signal output from said second state holding part, and outputting a signal indicating said state thus held;
a state inverting part responsive to a predetermined state detection signal for outputting to said first state holding part a signal indicating a state which is different from the state indicated by the signal output from said second state holding part;
a state detection signal outputting part comparing the states of the respective signals output from said first state holding part and said third state holding part, outputting the state detection signal when said states are different from one another, and outputting a state non-detection signal when said states are same as one another; and
a state detection signal clearing part comparing the states of the respective signals output from said first state holding part and said second state holding part, and outputting a state detection signal clearing signal when said states are different from one another.
5. A state indicating information setting circuit comprising:
a first flip-flop circuit taking an input signal when a register read out signal has an L level;
a second flip-flop circuit taking a signal output from said first flip-flop circuit when the register read out signal has an H level;
a third flip-flop circuit taking a signal output from said second flip-flop circuit when the register read out signal has the L level;
a first exclusive-OR circuit performing an exclusive-OR operation between an output of said second flip-flop circuit and a predetermined state detection signal, and outputting a result of the exclusive-OR operation;
a second exclusive-OR circuit performing an exclusive-OR operation between an output of said first flip-flop circuit and an output of said second flip-flop circuit, and outputting a result of the exclusive-OR operation; and
a third exclusive-OR circuit performing an exclusive-OR operation between an output of said first flip-flop circuit and an output of said third flip-flop circuit, and outputting a result of the exclusive-OR operation as a state bit signal.
6. A status bit setting circuit comprising:
an inverting output part generating an output which is inverted each time when a predetermined status is detected;
state inversion transition parts having states inverted in sequence by the output of said inverting output part; and
a status bit setting part setting a predetermined status bit by detecting a process of propagation of the inversion transition in said state inversion transition parts.
7. The status bit setting circuit as claimed in claim 6, further comprising a status detection canceling part detecting the process of the inversion transition in said state inversion transition parts, and generating a signal canceling a status detection state.
8. The status bit setting circuit as claimed in claim 6, wherein:
said status bit setting part detects a completion of the propagation of the inversion transition and cancels the setting of the predetermined status bit.
9. The status bit setting circuit as claimed in claim 8, wherein:
said state inversion transition parts have the states alternately inverted in sequence in response to a rising edge and a decaying edge of a predetermined read out signal
10. The status bit setting circuit claimed in claim 6, further comprising a bus driver enabling reading out of the predetermined status bit externally only during an interval in which a predetermined read out signal is active.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A multi-package module comprising stacked first and second packages, each said package including a die attached to a substrate, wherein the substrate comprises a dielectric layer and a patterned metal layer wherein the second package is inverted, wherein the first and second substrates are interconnected by wire bonding, and wherein the first package comprises a flip-chip ball grid array package having a flip-chip in a die-up configuration.
2. The multi-package module of claim 1 wherein the inverted second package is a wire bonded land grid array package.
3. The multi-package module of claim 2 wherein the die and wire bonds in the inverted second package are at least partially encapsulated with a molding material.
4. The multi-package module of claim 2 wherein the die and wire bonds in the inverted second package are fully encapsulated with a molding material.
5. The multi-package module of claim 2 wherein the second package substrate is a single-metal layer substrate.
6. The multi-package module of claim 2 wherein the second package substrate is a bump chip carrier type package substrate.
7. The multi-package module of claim 1 wherein the flip chip package is provided with an electrical shield.
8. The multi-package module of claim 7 wherein the electrical shield is configured to serve as a heat spreader.
9. The multi-package module of claim 7 wherein the flip chip package includes an RF die, and the shield serves to limit electromagnetic interference between the RF die and other die in the multi-package module.
10. The multi-package module of claim 1 wherein the flip chip package includes an RF die.
11. The multi-package module of claim 1 wherein the first package is provided with an electrical shield.
12. The multi-package module of claim 1 wherein the inverted second package is a stacked die package.
13. The multi-package module of claim 12 wherein adjacent stacked die in the stacked die package are separated by spacers.
14. The multi-package module of claim 1 wherein the second package is stacked over the first package, and wherein the flip-chip die on the first package is provided with an electrical shield.
15. The multi-package module of claim 1 wherein the first package substrate includes an embedded ground plane.
16. The multi-package module of claim 15, the ground plane being configured to serve for heat dissipation.
17. The multi-package module of claim 15, the ground plane being configured to serve as an electrical shield.
18. The multi-package module of claim 1 wherein at least one of the first and the inverted second package is a stacked-die package.
19. The multi-package module of claim 1 wherein the inverted second package is a stacked-die package.
20. The multi-package module of claim 1, further comprising a heat shield.
21. A mobile communications device comprising a multi-package module according to claim 1, wherein the multi-package module is electrically connected to underlying circuitry in the mobile communications device.
22. A computer comprising a multi-package module according to claim 1, wherein the multi-package module is electrically connected to underlying circuitry in the computer.