What is claimed is:
1. A memory unit comprising:
a memory portion having storage units storing data bits;
a memory portion storing error correction bits;
an error checking and correction unit; and
registers to hold the location of one or more corrected bits.
2. The memory unit as recited in claim 1 wherein the error checking and correction unit includes circuitry for requesting an interrupt andor for setting a flag which can be polled, when a failing bit can be corrected.
3. The memory unit as recited in claim 1 wherein the error detection and correction unit includes circuitry for requesting an abort condition when a failing bit is detected which can not be corrected.
4. The memory unit as recited in claim 2 wherein the memory is composed of storage units storing data bits that can be set to one of two states, wherein any of the data bits may be changed to a first state independently of the other bits, the resulting state being a programmed state, wherein all of the data bits of a plurality of data bits must be set to the second state simultaneously, the second state being an erased state, the memory unit further comprising:
circuitry to store the location of a correctable error; and
circuitry to generate an interrupt request;
circuitry to set a flag bit only when the correctable error is a bit that has been changed from the programmed state to the erased state.
5. A memory unit comprising:
storage units storing data bits;
storage units storing error checking and correction bits; and
an error detection and correction unit wherein the memory unit contains circuitry to optionally exclude the condition where all of the data bits and error detection and correction bits are in the erased state from generating bit correction.
6. A memory unit comprising:
storage units for storing data bits;
storage units for storing error correction bits;
an error detection and correction unit;
circuitry to optionally exclude the condition where all of the data bits and error detection and correction bits are in the programmed state from generating bit correction.
7. A data processing system, the data processing system comprising:
a central processing unit; and
a memory unit, the memory unit including:
a main memory, the main memory storing data signal groups in a plurality of addresses;
an error checking and correction memory, the error checking and correction memory storing error correcting signals for each data signal group in the main memory at the same address in the error checking and correction code memory;
error checking and correction apparatus for identifying and correcting at least one error in a data group accessed by a read operation; and
failing bit apparatus, the failing bit apparatus identifying when a correctable error is the result of a failing location.
8. The data processing system as recited in claim 7 wherein the failing bit apparatus includes:
an address storage unit;
a correction pattern storage unit; and
an interrupt flag unit, the interrupt flag unit issuing an interrupt flag when an error is detected that can be the result of failing bit memory location.
9. The data processing system as recited in claim 8 further comprising an all logic 1s detection unit for determining whether all of the signals from a main memory and error checking and correction memory are all logic 1.
10. The data processing system as recited in claim 7 wherein the main memory and the error checking and correction memory are implemented in a technology selected from the group consisting of flash technology and EEPROM technology.
11. A method of responding to an error in a signal group retrieved from a non-volatile memory unit, the method comprising:
when the error is correctable, correcting the error in the signal group using error checking and correction techniques; and
when the error is consistent with a failing bit position, restoring the charge associated with the bit position.
12. The method as recited in claim 11 wherein the restoring step includes the steps of:
storing the address of the signal group having the error;
storing the correction pattern identifying location of the error in the signal group; and
providing an interrupt flag to the central processing unit indicating the need to restore a bit location in the memory unit.
13. The method as recited in claim 11 further comprising implementing the main memory and the error checking and correction memory in a technology selected from the group consisting of flash technology and EEPROM technology.
14. A memory unit comprising:
a non-volatile main memory unit;
a non-volatile error memory for storing error checking and correction signals for a signal group in the main memory having the same address;
error checking and correction apparatus, the error apparatus generating a correction pattern identifying the location of an error in an addressed signal group and the associated error signals, the error apparatus generating a restore signal when the error is consistent with a failing bit location;
flag apparatus storing the associated correction pattern and the associated address in response to the restore signal, the flag apparatus generating an interrupt flag in response to the restore signal.
15. The memory unit as recited in claim 14 wherein the stored correction pattern and the stored address are transferred to the central processor for restoration of the failing bit location when the central processing unit services the interrupt.
16. The memory unit as recited in claim 14 wherein the error checking and correction apparatus includes an all logic 1s detection unit, the all logic 1s detection unit determining when the signals stored in the main memory and in the error signal memory are all logic 1s.
17. The memory unit as recited in claim 14 wherein the main memory and the error checking and correction memory are implemented in a technology selected from the group consisting of flash technology and EEPROM technology.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method, including:
receiving a first document including a plurality of items;
breaking the first document into a plurality of subdocuments corresponding to the plurality of items; and
indexing each of the plurality of subdocuments into an index.
2. The method of claim 1, wherein the receiving includes crawling a network and retrieving one or more documents including the first document.
3. The method of claim 1, wherein the breaking of the document includes identifying one or more breaks, each break associated with a boundary between each one of the plurality of items.
4. The method of claim 3, wherein the identifying of the one or more breaks includes parsing data of the first document.
5. The method of claim 3, wherein the identifying of the one or more breaks includes rendering the document and processing one or more image attributes.
6. The method of claim 3, wherein the plurality of items includes item data associated with at least one selected from a list including products, services, reviews, and events.
7. The method of claim 1, wherein the indexing of the plurality of subdocuments includes appending document context data as metadata to at least one of the plurality of subdocuments.
8. The method of claim 7, including automatically extracting the document context data from the first document.
9. The method of claim 1, including:
receiving a query including search data from a user;
matching the search data to index data stored in the index; and
retrieving one or more subdocuments based on the subdocuments associated with the index data.
10. A system, including:
a processing module to receive a first document including a plurality of items;
a break module to break the document into a plurality of subdocuments corresponding to the plurality of items; and
an index module to index each of the plurality of subdocuments.
11. The system of claim 10, including a crawler module to crawl a network and return one or more documents including the first document.
12. The system of claim 10, wherein the break module to break the document includes the break module to identify one or more breaks by analyzing the first document structure to identify item data associated with each item of the plurality of items.
13. The system of claim 12, wherein the break module to analyze the first document structure to identify the item data includes the break module to apply text segmentation to the first document.
14. The system of claim 12, wherein the break module to identify the one or more breaks includes the break module to apply an HTML format analysis to the first document.
15. The system of claim 10, wherein the index module to index the plurality of subdocuments includes the index module to append document context data to at least one of the plurality of subdocuments.
16. The system of claim 15, including the index module to automatically extract the document context data from one or more subdocuments and to append corresponding document context data as metadata to each of the one or more subdocuments.
17. The system of claim 10, including:
a search module to receive a query including search data from a user; and
a list module match the search data to index data stored in the index and to retrieve one or more subdocuments based on the subdocuments associated with the index data.
18. A machine-readable medium embodying instructions which, when executed by a machine, cause the machine to:
receive a document including a plurality of items;
break the document into a plurality of subdocuments corresponding to the plurality of items; and
index each of the plurality of subdocuments.
19. The machine-readable medium of claim 18, the instructions to further cause the machine to identify one or more breaks by analyzing the first document structure to identify item data associated with each item of the plurality of items.
20. The machine-readable medium of claim 18, the instructions to further cause the machine to automatically extract the document context data from one or more subdocuments and to append corresponding document context data as metadata to each of the one or more subdocuments.