1. A resist composition consisting essentially of:
a thermoelastic polymer selected from the group consisting of: a styrene-ethylene copolymer, a styrene-ethylene block copolymer, a styrene-ethylene-butylene block copolymer, a styrene-isoprene copolymer, a styrene-butadiene copolymer, a styrene-butadiene block copolymer, a maleic anhydride-grafted styrene-ethylene block copolymer, a sulfonated styrene-alkylene block copolymer, an acrylonitrile-styrene-ethylene block copolymer, an arylene-vinylene copolymer, a polyethyleneimine polymer, methylmethacrylate-butadiene copolymer, and combinations thereof,
wherein the thermoelastic polymer has a Young’s Modulus of 20 MPa or less,
wherein the thermoelastic polymer has a molecular weight of 60,000 Da to 130,000 Da,
wherein the thermoelastic polymer is present in a concentration of 0.1% to 10% by weight; and
one or more solvents in which the thermoelastic polymer has a solubility of at least 1 mgmL, wherein the one or more solvents have a boiling point of 35\xb0 C. to 200\xb0 C.
2. The resist composition of claim 1, wherein a film or pattern prepared from the resist composition having a thickness of 100 nm absorbs 10% or less of radiation having a wavelength of about 250 nm to about 800 nm.
3. The resist composition of claim 1, wherein the resist composition has a viscosity of 0.5 cP to 10 cP.
4. The resist composition of claim 1, wherein the thermoelastic polymer has a melting point of 80\xb0 C. to 125\xb0 C.
5. The resist composition of claim 1, wherein the thermoelastic polymer has a Tg of \u221260\xb0 C. to \u221230\xb0 C.
6. The resist composition of claim 1, wherein the thermoelastic polymer is a styrene-ethylene-butylene block copolymer having a molecular weight of about 118,000 Da.
7. The resist composition of claim 1, wherein the thermoelastic polymer is an ethoxylated polyethyleneimine polymer having a molecular weight of about 70,000 Da.
8. The resist composition of claim 1, wherein the solvent is selected from the group consisting of: benzene, toluene, a xylene, cumene, mesitylene, propylene glycol mono-methyl ether, tetrahydrofuran, acetone, ethylacetate, methylethylketone, methylene chloride, 1,2-dichloroethane, chloroform, dimethylformamide, and combinations thereof.
9. A method for forming a feature on a substrate, the method comprising:
applying a resist composition comprising a thermoelastic polymer to a surface of a stamp to provide a coated stamp, wherein the stamp comprises a flexible material and has a surface including at least one indentation therein, the indentation being contiguous with and defining a pattern in the surface of the stamp;
contacting the coated stamp with a substrate for an amount of time and at a temperature sufficient to transfer the thermoelastic polymer from the stamp surface to the substrate, wherein the thermoelastic polymer covers the substrate in a pattern according to the pattern in the surface of the stamp;
separating the stamp from the substrate; and
reacting an area of the substrate not covered by the thermoelastic polymer pattern to a reactive composition to form a feature thereon,
wherein the pattern in the surface of the stamp defines a lateral dimension of the feature.
10. The method of claim 9, wherein the thermoelastic polymer has a Young’s Modulus of 1 MPa to 20 MPa.
11. The method of claim 9, wherein the thermoelastic polymer has a Tg of 25\xb0 C. or less.
12. The method of claim 11, wherein the thermoelastic polymer comprises a second polymer having a Tg of 25\xb0 C. or greater.
13. The method of claim 9, wherein the thermoelastic polymer is selected from the group consisting of: a styrene-butadiene copolymer, a styrene-isoprene copolymer, a polystyrene-poly(ethylenebutylene)-polystyrene triblock copolymer grafted with maleic anhydride, and combinations thereof.
14. The method of claim 9, further comprising annealing the thermoelastic polymer on the surface of the stamp, the substrate, or a combination thereof.
15. The method of claim 9, wherein the temperature of at least one of the stamp, the substrate, and the thermoelastic polymer is maintained at or above a Tg of the thermoelastic polymer during the contacting.
16. The method of claim 9, wherein the substrate is maintained at a temperature at or below a Tg of the thermoelastic polymer during the reacting.
17. The method of claim 9, wherein the substrate is maintained at a temperature of 30\xb0 C. to 150\xb0 C. during the reacting.
18. The method of claim 9, wherein the reacting is performed for 0.5 seconds to 300 seconds.
19. The method of claim 9, further comprising removing the thermoelastic polymer pattern from the substrate.
20. The method of claim 9, wherein the reacting further comprises exposing the substrate to a reaction initiator selected from the group consisting of: thermal energy, radiation, acoustic waves, a plasma, an electron beam, a stoichiometric chemical reagent, a catalytic chemical reagent, a reactive gas, an increase or decrease in pH, an increase or decrease in pressure, electrical current, agitation, friction, and combinations thereof.
21. The method of claim 9, wherein the reactive composition comprises a species selected from the group consisting of: an acid, a base, a halogen-containing compound, a halide, and combinations thereof.
22. A composition comprising: a stamp comprising a flexible material, the stamp having a surface including at least one indentation therein, the indentation being contiguous with and defining a pattern in the surface of the stamp, and the surface of the stamp having a resist composition thereon, the resist composition comprising a thermoelastic polymer having a Young’s Modulus of 20 MPa or less and a molecular weight of 60,000 Da to 130,000 Da.
23. The composition of claim 22, wherein the coating on the stamp surface absorbs 10% or less of radiation having a wavelength of about 250 nm to about 800 nm for 100 nm of pattern thickness.
24. The composition of claim 22, wherein the thermoelastic polymer has a melting point of 80\xb0 C. to 125\xb0 C.
25. The composition of claim 22, wherein the thermoelastic polymer has a Tg of \u221260\xb0 C. to \u221230\xb0 C.
26. The composition of claim 22, wherein the resist composition has a thickness of 25 nm to 10 \u03bcm and forms a discontinuous coating on the stamp.
27. A composition comprising: a substrate having a thermoelastic polymer pattern thereon, wherein the pattern has at least one spacing of 50 \u03bcm or less, the thermoelastic polymer has a Young’s Modulus of 20 MPa or less and a molecular weight of 60,000 Da to 130,000 Da, and the pattern absorbs 10% or less of radiation having a wavelength of about 250 nm to about 800 nm for 100 nm of pattern thickness.
28. The composition of claim 27, wherein the thermoelastic polymer has a melting point of 80\xb0 C. to 125\xb0 C.
29. The composition of claim 27, wherein the thermoelastic polymer has a Tg of \u221260\xb0 C. to \u221230\xb0 C.
30. The composition of claim 27, wherein the pattern has a vertical dimension of 25 nm to 10 \u03bcm.
31. The composition of claim 27, wherein the pattern has 2 defects or less per 100 features.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A nonvolatile semiconductor memory device comprising:
a semiconductor substrate;
a trench isolation provided in the semiconductor substrate, the trench isolation defining an active area at the semiconductor substrate, the active area extending in a first direction;
an interlayer insulator provided on the semiconductor substrate, the interlayer insulator having a wiring trench, the wiring trench extending in a second direction intersecting the first direction;
a first conductive material layer provided at a cross-point of the active area and the wiring trench, the first conductive material layer being insulated from the active area;
a second conductive material layer provided in the wiring trench, the second conductive material layer being insulated from the first conductive material layer; and
a metal layer provided in the wiring trench, the metal layer electrically contacting the second conductive material layer.
2. The device according to claim 1, wherein a side surface of the first conductive material layer contacts a side surface of the trench isolation.
3. The device according to claim 2, wherein a position of a top surface of the first conductive material layer is higher than a position of a top surface of the trench isolation.
4. The device according to claim 1, wherein a position of a top surface of the metal layer and a position of a top surface of the interlayer insulator coincide with each other.
5. The device according to claim 1, wherein the first and second conductive material layers contain conductive polysilicon.
6. The device according to claim 1, wherein the metal layer contains tungsten.
7. The device according to claim 1, wherein the first conductive material layer, the second conductive material layer, and the metal layer form stacked gates of a memory cell transistor.
8. The device according to claim 7, wherein the first conductive material layer is a floating gate, and the second conductive material layer and the metal layer are control gates.
9. The device according to claim 7, wherein the metal layer functions as a word line.
10. A nonvolatile semiconductor memory device comprising:
a semiconductor substrate;
a trench isolation provided in the semiconductor substrate, the trench isolation defining an active area at the semiconductor substrate, the active area extending in a first direction;
an interlayer insulator provided on the semiconductor substrate, the interlayer insulator having first and second wiring trenches, the first and second wiring trenches extending in a second direction intersecting the first direction;
a first conductive material layer provided at cross-points of the active area and the first and second wiring trenches, the first conductive material layer being insulated from the active area;
a second conductive material layer provided in the first wiring trench, the second conductive material layer being insulated from the first conductive material layer; and
a metal layer provided in the first and second wiring trenches, the metal layer electrically contacting the second conductive material layer in the first wiring trench and electrically contacting the first conductive material layer in the second wiring trench.
11. The device according to claim 10, wherein a side surface of the first conductive material layer contacts a side surface of the trench isolation.
12. The device according to claim 11, wherein a position of a top surface of the first conductive material layer is higher than a position of a top surface of the trench isolation.
13. The device according to claim 10, wherein a position of a top surface of the metal layer and a position of a top surface of the interlayer insulator coincide with each other.
14. The device according to claim 10, wherein the first and second conductive material layers contain conductive polysilicon.
15. The device according to claim 10, wherein the metal layer contains tungsten.
16. The device according to claim 10, wherein the first conductive material layer, the second conductive material layer, and the metal layer form stacked gates of a memory cell transistor in the first wiring trench, and the first conductive material layer and the metal layer form gates of a select transistor in the second wiring trench.
17. The device according to claim 16, wherein, in the first wiring trench, the first conductive material layer is a floating gate and the second conductive material layer and the metal layer are control gates.
18. The device according to claim 16, wherein the second conductive material layer and the metal layer function as word lines in the first wiring trench, and the metal layer functions as a select gate line in the second wiring trench.
19. A nonvolatile semiconductor memory device comprising:
a semiconductor substrate;
a trench isolation provided in the semiconductor substrate, the trench isolation defining first and second active areas at the semiconductor substrate, the first active area extending in a first direction and the second active area extending in a second direction;
an interlayer insulator provided on the semiconductor substrate, the interlayer insulator having first and second wiring trenches, the first wiring trench extending in a third direction intersecting the first direction and the second wiring trench extending in a fourth direction intersecting the second direction;
a first conductive material layer provided at each of a cross-point of the first active area and the first wiring trench and a cross-point of the second active area and the second wiring trench, the first conductive material layer being insulated from the first and second active areas;
a second conductive material layer provided in the first wiring trench, the second conductive material layer being insulated from the first conductive material layer; and
a metal layer provided in the first and second wiring trenches, the metal layer electrically contacting the second conductive material layer in the first wiring trench and electrically contacting the first conductive material layer in the second wiring trench.
20. The device according to claim 19, wherein a side surface of the first conductive material layer contacts a side surface of the trench isolation.
21. The device according to claim 20, wherein a position of a top surface of the first conductive material layer is higher than a position of a top surface of the trench isolation.
22. The device according to claim 19, wherein a position of a top surface of the metal layer and a position of a top surface of the interlayer insulator coincide with each other.
23. The device according to claim 19, wherein the first and second conductive material layers contain conductive polysilicon.
24. The device according to claim 19, wherein the metal layer contains tungsten.
25. The device according to claim 19, wherein the first conductive material layer, the second conductive material layer, and the metal layer form stacked gates of a memory cell transistor in the first wiring trench, and the first conductive material layer and the metal layer form gates of a peripheral transistor in the second wiring trench.
26. The device according to claim 25, wherein, in the first wiring trench, the first conductive material layer is a floating gate, and the second conductive material layer and the metal layer are control gates.
27. The device according to claim 25, wherein the second conductive material layer and the metal layer function as word lines in the first wiring trench, and the metal layer functions as wiring of a peripheral circuit in the second wiring trench.
28. A nonvolatile semiconductor memory device comprising:
a semiconductor substrate;
a trench isolation provided in the semiconductor substrate, the trench isolation defining first and second active areas at the semiconductor substrate and the first active area extending in a first direction, the second active area extending in a second direction;
an interlayer insulator provided on the semiconductor substrate, the interlayer insulator having first, second, and third wiring trenches, the first and second wiring trenches extending in a third direction intersecting the first direction, and the third wiring trench extending in a fourth direction intersecting the second direction;
a first conductive material layer provided at each of cross-points of the first active area and the first and second wiring trenches and a cross-point of the second active area and the third wiring trench, the first conductive material layer being insulated from the first and second active areas;
a second conductive material layer provided in the first wiring trench, the second conductive material layer being insulated from the first conductive material layer; and
a metal layer provided in the first, second, and third wiring trenches, the metal layer electrically contacting the second conductive material layer in the first wiring trench and electrically contacting the first conductive material layer in the second and third wiring trenches.
29. The device according to claim 28, wherein a side surface of the first conductive material layer contacts a side surface of the trench isolation.
30. The device according to claim 29, wherein a position of a top surface of the first conductive material layer is higher than a position of a top surface of the trench isolation.
31. The device according to claim 28, wherein a position of a top surface of the metal layer and a position of a top surface of the interlayer insulator coincide with each other.
32. The device according to claim 28, wherein the first and second conductive material layers contain conductive polysilicon.
33. The device according to claim 28, wherein the metal layer contains tungsten.
34. The device according to claim 28, wherein the first conductive material layer, the second conductive material layer, and the metal layer form stacked gates of a memory cell transistor in the first wiring trench, and the first conductive material layer and the metal layer form gates of a select transistor in the second wiring trench, and the first conductive material layer and the metal layer form gates of a peripheral transistor in the third wiring trench.
35. The device according to claim 34, wherein, in the first wiring trench, the first conductive material layer is a floating gate and the second conductive material layer and the metal layer are control gates.
36. The device according to claim 34, wherein the second conductive material layer and the metal layer function as word lines in the first wiring trench, the metal layer functions as a select gate line in the second wiring trench, and the metal layer functions as wiring of a peripheral circuit in the third wiring trench.
37. A method for manufacturing a nonvolatile semiconductor memory device comprising:
forming a first stacked structure including at least a gate insulator and a first conductive material layer on a semiconductor substrate;
forming trenches corresponding to a pattern of element isolation regions from the first stacked structure into the semiconductor substrate;
forming an insulating material in the trenches;
forming a second stacked structure including at least an inter-gate insulator and a second conductive material layer on the exposed surfaces of the insulating material and the first stacked structure;
forming a plurality of stacked gate structures including at least the first conductive material layer, a second gate insulator, and the second conductive material layer by patterning the first stacked structure and the second stacked structure;
forming an interlayer insulator between the stacked gate structures;
forming trenches corresponding to the pattern of the stacked gate structures at the interlayer insulator by partially removing the stacked gate structure; and
forming a third conductive material layer in the trenches.
38. The method according to claim 37, wherein the forming of trenches corresponding to a pattern of the stacked gate structures comprises:
a process of, in the stacked gate structure corresponding to the memory cell transistor among the stacked gate structures, removing the stacked gate structure such that the second conductive material layer is exposed at the bottom of the trench.
39. The method according to claim 37, wherein the forming of trenches corresponding to a pattern of the stacked gate structures comprises:
a process of, in the stacked gate structure corresponding to the select transistor among the stacked gate structures, removing the stacked gate structure such that the first conductive material layer is exposed at the bottom of the trench.
40. The method according to claim 37, wherein the forming of trenches corresponding to a pattern of the stacked gate structures comprises:
a process of, in the stacked gate structure corresponding to the peripheral transistor among the stacked gate structures, removing the stacked gate structure such that the first conductive material layer is exposed at the bottom of the trench.