1. A transistor comprising:
a first semiconductor layer;
a second semiconductor layer located on the first semiconductor layer, a portion of the second semiconductor layer being removed to expose a first portion of the first semiconductor layer and provide vertical sidewalls of the second semiconductor layer;
a gate spacer located on the second semiconductor layer;
a gate dielectric comprising a first portion located on the first portion of the first semiconductor layer and a second portion adjacent to the vertical sidewalls of the second semiconductor layer and vertical sidewalls of the gate spacer;
a gate conductor located on the first portion of the gate dielectric and abutting the second portion of the gate dielectric, the gate conductor comprising a metal layer located on the first portion of the gate dielectric and a gate polysilicon layer located on the metal layer;
a channel region located in at least part of the first portion of the first semiconductor layer; and
raised sourcedrain regions located in the second semiconductor layer, at least part of the raised sourcedrain regions being located below the gate spacer.
2. The transistor of claim 1, further comprising:
a substrate; and
a buried oxide layer above the substrate, the first semiconductor layer being located on the buried oxide layer.
3. The transistor of claim 1, wherein the first semiconductor layer comprises silicon and has a thickness of less than about 10 nanometers.
4. The transistor of claim 3, wherein the gate dielectric comprises a high-k dielectric material.
5. The transistor of claim 4, further comprising a dielectric spacer located between the second portion of the gate dielectric and the vertical sidewalls of the second semiconductor layer and the gate spacer.
6. The transistor of claim 4, wherein the second portion of the gate dielectric is located on the vertical sidewalls of the second semiconductor layer and the gate spacer.
7. The transistor of claim 4, further comprising sourcedrain extension regions located in the first semiconductor layer below the raised sourcedrain regions.
8. The transistor of claim 4, where the second semiconductor layer comprises silicon-germanium.
9-24. (canceled)
25. The transistor of claim 1, further comprising an epitaxial layer located on the second semiconductor layer, the raised source drain regions comprising the epitaxial layer.
26. A transistor comprising:
a first semiconductor layer;
a second semiconductor layer located on the first semiconductor layer, a portion of the second semiconductor layer being removed to expose a first portion of the first semiconductor layer and provide vertical sidewalls of the second semiconductor layer;
a gate spacer located on the second semiconductor layer;
a gate dielectric comprising a first portion located on the first portion of the first semiconductor layer and a second portion adjacent to the vertical sidewalls of the second semiconductor layer and vertical sidewalls of the gate spacer;
a gate conductor located on the first portion of the gate dielectric and abutting the second portion of the gate dielectric;
a channel region located in at least part of the first portion of the first semiconductor layer;
raised sourcedrain regions located in the second semiconductor layer, at least part of the raised sourcedrain regions being located below the gate spacer; and
silicide areas, one of the silicide areas being located on each of the raised sourcedrain regions,
wherein the silicide areas comprise metal silicide.
27. The transistor of claim 26, wherein the gate conductor comprises a metal layer located on the first portion of the gate dielectric and a gate polysilicon layer located on the metal layer.
28. The transistor of claim 27, further comprising an epitaxial layer located on the second semiconductor layer, the raised source drain regions comprising the epitaxial layer.
29. The transistor of claim 26, further comprising an epitaxial layer located on the second semiconductor layer, the raised source drain regions comprising the epitaxial layer.
30. A transistor comprising:
a first semiconductor layer;
a second semiconductor layer located on the first semiconductor layer;
a dummy gate stack located on the second semiconductor layer, the dummy gate stack comprising a dummy gate dielectric located on the second semiconductor layer, and a dummy gate conductor located on the dummy gate dielectric;
a gate spacer located on the second semiconductor layer and on sidewalls of the dummy gate stack;
sourcedrain regions located in the second semiconductor layer, part of the sourcedrain regions being located below the gate spacer;
sourcedrain extension regions located in the first semiconductor layer below the sourcedrain regions, the sourcedrain extension regions being doped; and
a channel region located in the first semiconductor layer between the sourcedrain extension regions.
31. The transistor of claim 30, wherein part of the gate spacer is located on top of the dummy gate stack.
32. The transistor of claim 30, wherein the dummy gate conductor is amorphous silicon.
33. The transistor of claim 30, wherein the dummy gate conductor is oxide or nitride.
34. The transistor of claim 33, wherein the dummy gate dielectric is polysilicon or amorphous silicon.
35. The transistor of claim 30, wherein the dummy gate dielectric is polysilicon or amorphous silicon.
36. The transistor of claim 30, wherein both the dummy gate dielectric and the dummy gate conductor are formed of one and only one of oxide, polysilicon, amorphous silicon, and nitride.
37. The transistor of claim 30, further comprising an epitaxial layer located on the second semiconductor layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device having a capacitor area and a wiring area selectively disposed on a semiconductor substrate, comprising:
an interlayer insulating film disposed above the semiconductor substrate;
a thin-film metal film that is disposed on the interlayer insulating film and that is in the capacitor area, the thin-film metal film serves as a bottom electrode of the capacitor;
a via that is formed in the interlayer insulating film and that contacts the thin-film metal film from below;
a wiring line that is disposed above the interlayer insulating film and that is in the wiring area;
a first dummy wiring line that is disposed in a wiring layer in the same layer as the wiring line and that covers the thin-film metal film from above, the first dummy wiring line serves as a top electrode of the capacitor; and
a capacitor dielectric film interposed between the thin-film metal film and the first dummy wiring line.
2. The semiconductor device according to claim 1, wherein the first dummy wiring line includes overlapping parts that cover the thin-film metal film from sides thereof.
3. The semiconductor device according to claim 1, wherein the capacitor dielectric film includes side walls that cover respective side faces of the thin-film metal film.
4. The semiconductor device according to claim 1, further comprising a second interlayer capacitor dielectric film formed on the interlayer insulating film so as to cover the wiring line and the first dummy wiring line,
wherein the second interlayer insulating film has a via hole formed therein selectively exposing a top of the first dummy wiring line.
5. The semiconductor device according to claim 1,
wherein the capacitor dielectric film is an SiO2 film, and
wherein the semiconductor device further includes a TiN layer interposed between the first dummy wiring line and the SiO2 film.
6. The semiconductor device according to claim 1,
wherein the capacitor dielectric film is an SiO2 film, and
wherein the interlayer insulating film has, on an outermost surface thereof, an etching stopper made of an insulating material that has etching selectivity with respect to SiO2.
7. The semiconductor device according to claim 6, wherein the etching stopper is made of an SiN film.
8. The semiconductor device according to claim 1, wherein the thin-film metal film is made of SiCr, NiCr, TaN, or TiN.
9. The semiconductor device according to claim 1, wherein the first dummy wiring line has a lamination structure that is same as the wiring line.
10. The semiconductor device according to claim 9, wherein both of the first dummy wiring line and the wiring line have a multilayer configuration including an Al alloy wiring line and barrier films that respectively sandwich said Al alloy wiring line from above and below.
11. The semiconductor device according to claim 1, further comprising a resistor area disposed on the semiconductor substrate,
wherein said resistor area includes:
a thin film resistor disposed on the interlayer insulating film;
a second dummy wiring line disposed in a wiring layer that is in the same layer as the wiring line, the second dummy wiring line facing the thin film resistor; and
an insulating film interposed between the thin film resistor and the second dummy wiring line.