1. A computing device comprising:
a multi-core processor having a particular number M of executing cores, each core being a discrete logical processing entity capable of individually being assigned work;
a multi-core application instantiated on the computing device and expecting a particular number N of executing cores to be present on the M-core processor, where N is not equal to M, the N-core application assigning N application work portions for processing; and
a virtual machine instantiated on the M-core processor, the N-core application being instantiated on the virtual machine, and the virtual machine emulating an N-core processor to the N-core application for processing of the N application work portions.
2. The computing device of claim 1 wherein each work portion as assigned by the application includes at least one thread.
3. The computing device of claim 1 wherein the virtual machine represents a partitioning of the computing device that isolates the application from other applications on such computing device.
4. The computing device of claim 1 wherein the virtual machine emulates a plurality of differing numbers N of cores of the processor for the application and wherein the virtual machine may be instantiated on any of a plurality of processors, each having a differing number M of cores.
5. The computing device of claim 1 wherein the virtual machine emulates the N cores of the processor for an application and wherein the virtual machine may be instantiated on any of a plurality of processors, each having a differing number M of cores.
6. The computing device of claim 1 wherein the cores of the processor are organized into pairs, each core of each pair of cores being coupled to a level 1 (L1) cache and the L1 caches of each pair of cores being coupled to a shared level 2 (L2) cache such that the pair of cores can communicate data directly therebetween by way of the shared L2 cache, and wherein the virtual machine in assigning a pair of work portions of the application to respective cores of the processor assesses how much interaction exists between the pair of work portions and assigns the pair of work portions based on such assessment, the virtual machine assigning a pair of work portions that interact a relatively large amount to a pair of cores of the processor that share an L2 cache, and assigning a pair of work portions that interact a relatively small amount to cores of the processor that do not share an L2 cache.
7. The computing device of claim 1 wherein the virtual machine in assigning work portions of the application to cores of the processor performs dynamic load balancing among the cores of the processor, the virtual machine assigning each work portion to a particular core based on an assessment of workload of such particular core.
8. The computing device of claim 1 wherein each core of the multi-core processor has a particular type selected from among a plurality of core types, wherein each work portion of the application has a particular type selected from among a plurality of work portion types, and wherein the virtual machine assigns each work portion of the application to a core of the processor according to the type of the work portion and the types of each core available from the processor.
9. The computing device of claim 8 wherein a first core of the processor is a specialized type of core that performs a corresponding specialized task and a second core is a general type of core that performs general tasks, wherein the virtual machine assigns a work portion that corresponds to the specialized task to the first core if such first core is available, and wherein the virtual machine assigns the work portion that corresponds to the specialized task to the second core if such first core is not available, the second core running an emulation for performing the specialized task.
10. A computer-readable medium having stored thereon computer-executable instructions for execution by a computing device having a multi-core processor having a particular number M of executing cores, each core being a discrete logical processing entity capable of individually being assigned work, the computer-executable instructions executed by the computing device comprising:
a multi-core application instantiated on the computing device for performing a processing function on input data, said multi-core application expecting a particular number N of executing cores to be present on the M-core processor, where N is not equal to M, the N-core application assigning N application work portions for processing the input data using N executing cores; and
a virtual machine instantiated on the M-core processor, the N-core application being instantiated on the virtual machine, and the virtual machine emulating an N-core processor to the N-core application for processing of the N application work portions.
11. The medium of claim 10 wherein the virtual machine represents a partitioning of the computing device that isolates the application from other applications on the computing device.
12. The medium of claim 10 wherein the virtual machine emulates a plurality of differing numbers N of cores of the processor for the application and wherein the virtual machine may be instantiated on any of a plurality of processors, each having a differing number M of cores.
13. The medium of claim 10 wherein the cores of the processor are organized into pairs, each core of each pair of cores being coupled to a level 1 (L1) cache and the L1 caches of each pair of cores being coupled to a shared level 2 (L2) cache such that the pair of cores can communicate data directly therebetween by way of the shared L2 cache, and wherein the virtual machine in assigning a pair of work portions of the application to respective cores of the processor assesses how much interaction exists between the pair of work portions and assigns the pair of work portions based on such assessment, the virtual machine assigning a pair of work portions that interact a relatively large amount to a pair of cores of the processor that share an L2 cache, and assigning a pair of work portions that interact a relatively small amount to cores of the processor that do not share an L2 cache.
14. The medium of claim 10 wherein the virtual machine in assigning work portions of the application to cores of the processor performs dynamic load balancing among the cores of the processor, the virtual machine assigning each work portion to a particular core based on an assessment of workload of such particular core.
15. The medium of claim 10 wherein each core of the multi-core processor has a particular type selected from among a plurality of core types, wherein each work portion of the application has a particular type selected from among a plurality of work portion types, and wherein the virtual machine assigns each work portion of the application to a core of the processor according to the type of the work portion and the types of each core available from the processor.
16. The medium of claim 15 wherein a first core of the processor is a specialized type of core that performs a corresponding specialized task and a second core is a general type of core that performs general tasks, wherein the virtual machine assigns a work portion that corresponds to the specialized task to the first core if such first core is available, and wherein the virtual machine assigns the work portion that corresponds to the specialized task to the second core if such first core is not available, the second core running an emulation for performing the specialized task.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated driver with improved load current sense capability, comprising:
a first transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor is coupled to one side of a load;
a first amplifier including a first input, a second input and an output, wherein the first input of the first amplifier is coupled to the first terminal of the first transistor;
a second transistor having a first terminal, a second terminal and a control terminal, wherein the control terminal of the second transistor is coupled to the output of the first amplifier, the first terminal of the second transistor is coupled to one side of a power source via a first impedance;
a third transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the third transistor is coupled to the second terminal of the second transistor and the second input of the first amplifier, and wherein the control terminals of the first and third transistors are coupled together and the first and third transistors conduct responsive to a control signal provided on the control terminals of the first and third transistors;
a second amplifier including a first input, a second input and an output, wherein the first input of the second amplifier is coupled to the first terminal of the second transistor; and
a fourth transistor including a first terminal, a second terminal and a control terminal, wherein the output of the second amplifier is coupled to the control terminal of the fourth transistor and the second input of the second amplifier is coupled to the second terminal of the fourth transistor, and wherein the second terminal of the fourth transistor is coupled to the one side of the power source via a second impedance and the first terminal of the fourth transistor provides an output current that is indicative of a load current through the load.
2. The driver of claim 1, wherein the load is a heater of an oxygen sensor.
3. The driver of claim 1, wherein an on-impedance of the third transistor is about five-hundred times an on-impedance of the first transistor.
4. The driver of claim 1, wherein the first transistor is a double-diffused metal-oxide semiconductor (DMOS) driver.
5. The driver of claim 4, wherein the DMOS driver has an on-impedance of about fifty milliOhms.
6. The driver of claim 1, wherein the first transistor has an on-impedance of about fifty milliOhms and the third transistor has an on-impedance of about twenty-five Ohms.
7. The driver of claim 1, wherein an impedance of the second impedance is about ten times an impedance of the first impedance.
8. An integrated driver with improved load current sense capability, comprising:
a first transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor is coupled to one side of a load;
a first amplifier including a first input, a second input and an output, wherein the first input of the first amplifier is coupled to the first terminal of the first transistor;
a second transistor having a first terminal, a second terminal and a control terminal, wherein the control terminal of the second transistor is coupled to the output of the first amplifier, the first terminal of the second transistor is coupled to one side of a power source via a first impedance;
a third transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the third transistor is coupled to the second terminal of the second transistor and the second input of the first amplifier, and wherein the control terminals of the first and third transistors are coupled together and the first and third transistors conduct responsive to a control signal provided on the control terminals of the first and third transistors;
a second amplifier including a first input, a second input and an output, wherein the first input of the second amplifier is coupled to the first terminal of the second transistor; and
a fourth transistor including a first terminal, a second terminal and a control terminal, wherein the output of the second amplifier is coupled to the control terminal of the fourth transistor and the second input of the second amplifier is coupled to the second terminal of the fourth transistor, and wherein the second terminal of the fourth transistor is coupled to the one side of the power source via a second impedance and the first terminal of the fourth transistor provides an output current that is indicative of a load current through the load, where an on-impedance of the third transistor is about five-hundred times an on-impedance of the first transistor.
9. The driver of claim 8, wherein the load is a heater of an oxygen sensor.
10. The driver of claim 8, wherein the first, second, third and fourth transistors are metal-oxide semiconductor field-effect transistors (MOSFETs).
11. The driver of claim 8, wherein the first transistor has an on-impedance of about fifty milliOhms.
12. The driver of claim 8, wherein the third transistor has an on-impedance of about twenty-five Ohms.
13. The driver of claim 8, wherein an impedance of the second impedance is about ten times an impedance of the first impedance.
14. A method for sensing a load current, comprising the steps of:
conducting a first current responsive to a load current provided to a load, wherein the first current is proportional to the load current and is less than the load current, and wherein the first current flows through a first impedance;
providing an output current to an external impedance responsive to the first current, wherein the output current is proportional to the first current and is less than the first current, and wherein the output current flows through a second impedance that is less than the first impedance; and
calculating the load current based upon the output current.
15. The method of claim 14, wherein the load is a heater of an oxygen sensor.
16. The method of claim 14, wherein a magnitude of the load current is about five-hundred times a magnitude of the first current.
17. The method of claim 16, wherein the magnitude of the first current is about ten times a magnitude of the output current.
18. The method of claim 14, wherein a magnitude of the load current is about five-thousand times a magnitude of the output current.
19. The method of claim 14, wherein a magnitude of the second impedance is larger than a magnitude of the first impedance.
20. The method of claim 19, wherein the magnitude of the second impedance is about ten times the magnitude of the first impedance.