1. A method for DRAM initialization of a computer system, comprising:
storing initialization parameters of at least one memory;
detecting condition of the memory by checking an output signal of a detection circuit, wherein the detection circuit comprises at least a first electric device and a second electric device, wherein the detection circuit is operated by a way comprising:
having the first electric device receiving an input signal from the memory and outputting a first signal in responding to the input signal, wherein the input signal represents whether the memory is installed;
having the second electric device receiving the first signal and outputting a second signal;
comparing the second signal and the input signal; and
identifying whether the second signal and the input signal are different in order to provide the output signal standing for the condition of the memory; and
reading the memory condition to initialize memory when booting if, when the memory condition has not changed.
2. The method for DRAM initialization as claimed in claim 1, further comprising setting the initialization parameters according to memory information.
3. The method for DRAM initialization as claimed in claim 2, wherein the memory information is obtained by detecting serial presence detect codes thereof.
4. The method for DRAM initialization as claimed in claim 1, wherein the unchanged memory condition indicates no memory is changed.
5. The method for DRAM initialization as claimed in claim 1, wherein the unchanged memory condition indicates no memory is removal.
6. The method for DRAM initialization as claimed in claim 1, wherein the initialization parameters of the memory is stored in a buffer.
7. The method for DRAM initialization as claimed in claim 1, wherein the initialization parameters of the memory comprise at least operating frequency or column address strobe latency of the memory.
8. The method for DRAM initialization as claimed in claim 1, wherein the initialization of the memory comprises setting at least operating frequency or column address strobe latency of the memory.
9. The method for DRAM initialization as claimed in claim 1, wherein more than one memory is applied.
10. The method for DRAM initialization as claimed in claim 9, wherein the unchanged memory condition indicates no memory is removal.
11. A device for DRAM initialization of a computer system, comprising:
at least one memory;
a detection circuit detecting condition of the memory, and outputting a fast initialization signal, wherein the detection circuit comprises:
a first electric device receiving an input signal representing whether the memory is installed, and outputting a first signal in responding to the input signal;
a second electric device receiving the first signal, and outputting a second signal in responding to an output signal; and
a third electric device coupled between the first electric device and the second electric device and also outputting the output signal in responding to the input signal and the second signal, wherein the output signal is regarded as the fast initialization signal when the condition of the memory is not changed;
a buffer storing initialization parameters of at least one memory; and
a memory controller setting the initialization parameters according to memory information, and reading the memory condition to initialize the memory when booting and receiving the fast initialization signal.
12. The device for DRAM initialization as claimed in claim 11, wherein the memory information is obtained by detecting serial presence detect codes of the memory.
13. The device for DRAM initialization as claimed in claim 11, wherein the unchanged memory condition indicates no memory is changed.
14. The device for DRAM initialization as claimed in claim 11, wherein the unchanged memory condition indicates no memory is removal.
15. The device for DRAM initialization as claimed in claim 11, wherein the buffer is located in a Southbridge chipset.
16. The device for DRAM initialization as claimed in claim 11, wherein the initialization parameters of the memory comprise at least operating frequency or column address strobe latency of the memory.
17. The device for DRAM initialization as claimed in claim 11, wherein the initialization of the memory comprises setting at least operating frequency or column address strobe latency of the memory.
18. The device for DRAM initialization as claimed in claim 11, wherein more than one memory is applied.
19. The device for DRAM initialization as claimed in claim 18, wherein the unchanged memory condition indicates no memory is removal.
20. The device for DRAM initialization as claimed in claim 11, wherein the first electric device is a first flip-flop, and the first flip-flop comprises a first clock terminal receiving the input signal inverted by an inverter.
21. The device for DRAM initialization as claimed in claim 11, wherein the second electric device is a second flip-flop, and the second flip-flop comprises a second clock terminal receiving the output signal.
22. The device for DRAM initialization as claimed in claim 11, wherein the third electric device is a comparator, and the comparator is an XOR logic gate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A compound of the formula (I)
in which
W represents cyano, halogen, alkyl, alkenyl, alkynyl, alkoxy, haloalkyl or haloalkoxy,
X represents hydrogen, halogen, alkyl, alkoxy, haloalkyl, haloalkoxy or cyano,
Y represents hydrogen, halogen, alkyl, alkoxy, haloalkyl, haloalkoxy or cyano,
Z represents hydrogen, halogen, alkyl, alkoxy, haloalkyl, haloalkoxy or cyano,
A represents O,
B represents CH2,
G represents halogen or nitro,
R3 represents hydrogen or C1-C4-alkyl, and
Q represents NH.
2. A compound of the formula (I) according to claim 1 in which
A represents O,
B represents CH2,
W represents fluorine, chlorine, bromine, C1-C4-alkyl, C1-C4-alkoxy, C1-C2-haloalkyl, C1-C2-haloalkoxy or cyano,
X represents hydrogen, fluorine, chlorine, bromine, C1-C4-alkyl or C1-C4-alkoxy,
Y represents hydrogen, fluorine, chlorine, bromine, C1-C4-alkyl, C1-C2-haloalkyl, C1-C2-haloalkoxy or cyano,
Z represents hydrogen, fluorine, chlorine, bromine, C1-C4-alkyl, C1-C4-alkoxy, C1-C2-haloalkyl, C1-C2-haloalkoxy or cyano,
G represents chlorine, bromine or nitro,
R3 represents hydrogen, and
Q represents NH.
3. A compound of the formula (I) according to claim 1 in which
A represents O,
B reDresents CH2,
W represents chlorine, bromine, methyl, ethyl, propyl, methoxy, ethoxy, trifluoromethyl, difluoromethoxy, trifluoromethoxy or cyano,
X represents hydrogen, chlorine, bromine, methyl, ethyl, propyl, methoxy or ethoxy,
Y represents hydrogen, chlorine, bromine, methyl, ethyl, propyl, trifluoromethyl, trifluoromethoxy, difluoromethoxy or cyano,
Z represents hydrogen, fluorine, chlorine, bromine, methyl, ethyl, propyl, methoxy, ethoxy, trifluoromethyl, trifluoromethoxy, difluoromethoxy or cyano,
G represents chlorine, bromine or nitro,
R3 represents hydrogen, and
Q represents NH.
4. A compound of the formula (I) according to claim 1 in which
A represents O,
B represents Ch2,
W represents chlorine, bromine, methyl or ethyl,
X represents hydrogen, chlorine, methyl or ethyl,
Y represents hydrogen, chlorine, bromine, methyl or ethyl,
Z represents hydrogen, chlorine or methyl,
G represents chlorine,
R3 represents hydrogen, and
Q represents NH.
5. A compound of the formula (I) according to claim 1 in which
A represents O,
B represents CH2,
W represents methyl,
X represents hydrogen, methyl or chlorine,
Y represents hydrogen, methyl, chlorine or bromine,
Z represents hydrogen, methyl or chlorine,
C represents chlorine or nitro,
R3 represents hydrogen, and
Q represents NH.
6. A process for preparing a compound of the formula (I) according to claim 1, comprising
A) when the compound is a compound of the formulae (I-1) to (I-3)
in which
A, B, W, X, Y, Z and R3 are as defined in claim 1 and
G represents halogen,
reacting a compound of the formulae (II-1)
in which
A, B, W, X, Y, Z and R3 are as defined above,
with one or more halogenating agents in the presence of a solvent and, optionally, in the presence of a radical initiator;
B) when the compound is a compound of the formulae (I-1)
in which
A, B, W, X, Y, Z and R3 are as defined above and
G represents nitro,
reacting a compound of the formulae (II-1),
in which
A, B, W, X, Y, Z and R3 are as defined above
with one or more nitrating agents in the presence of a solvent.
7. A process for preparing a compound of the formula (I) according to claim 1, comprising employing a compound of the formula (II)
in which
A, B, Q, W, X, Y, Z and R3 are as defined in claim 1 in the preparation of said compound of the formula (I) according to claim 1.
8. A pesticide, herbicide andor a fungicide comprising at least one compound of the formula (I) according to claim 1.
9. A method for controlling animal pests, unwanted vegetation andor fungi comprising allowing a compound of the formula (I) according to claim 1 to act on said pests, said vegetation, said fungi andor their habitat.
10. A process for preparing a pesticide, a herbicide andor a fungicide comprising mixing a compound of the formula (I) according to claim 1 with one or more extenders andor surfactants.