1. An electrical connector assembly comprising:
an interposer having a side surface and an array of electrical contacts that are exposed to an external space along the side surface, the electrical contacts being configured to engage an electronic module mounted over the side surface; and
a shield wall attached to and extending along the side surface, the shield wall having a wall body that extends away from the side surface into the external space along the interposer, the shield wall separating the external space into shielded sub-regions, the shield wall including a conductive material and being electrically coupled to the interposer, wherein at least one electrical contact is located within each shielded sub-region, the shield wall extending between adjacent electrical contacts to shield the adjacent electrical contacts from electromagnetic interference.
2. The electrical connector assembly of claim 1, wherein the shield wall is stamped or etched from conductive material.
3. The electrical connector assembly of claim 2, wherein the shield wall is stamped from a sheet of the conductive material and mechanically coupled to the interposer, the shield wall projecting orthogonal to the side surface.
4. The electrical connector assembly of claim 1, wherein the connector assembly includes a plurality of the shield walls, the plurality of shield walls forming a shielding matrix.
5. The electrical connector assembly of claim 1, wherein at least 75% of the electrical contacts in the array are signal contacts configured to have data signals transmitted therethrough.
6. The electrical connector assembly of claim 1, wherein the shield wall has a module edge that is exposed to the external space and configured to interface with the electronic module, the shield wall including a grounding feature that is located along the module edge, the grounding feature being shaped from the wall body and configured to engage the electronic module, wherein a ground pathway exists through the grounding feature to the interposer.
7. The electrical connector assembly of claim 1, wherein the side surface is a first side surface and the interposer includes a second side surface that faces in an opposite direction than the first side surface, the shield wall having a mounting projection that extends through the interposer and is electrically coupled to an electrical contact that is exposed along the second side surface.
8. The electrical connector assembly of claim 1, wherein the electrical contacts include beams that project away from the side surface into the external space, at least a portion of the beams extending away from the side surface at a non-orthogonal angle.
9. The electrical connector assembly of claim 1, wherein the wall body has opposite sides with a thickness of the wall body extending therebetween, the thickness being substantially uniform, wherein the sides of the wall body are exposed to the external space and define the shielded sub-regions.
10. The electrical connector assembly of claim 1, wherein the interposer has a plurality of stacked layers including a conductive layer that is etched to form the wall body of the shield wall.
11. The electrical connector assembly of claim 1, wherein the shield wall includes a plurality of mounting projections that directly engage the interposer and mechanically couple the interposer and the shield wall.
12. An electrical connector assembly comprising:
an interposer having a side surface and an array of electrical contacts that are exposed to an external space along the side surface, the electrical contacts being configured to engage an electronic module mounted over the side surface; and
a shield wall attached to and extending along the side surface, the shield wall having a wall body that extends away from the side surface into the external space along the interposer, the shield wall separating the external space into shielded sub-regions, the shield wall including a conductive material and being electrically coupled to the interposer, wherein at least one electrical contact is located within each shielded sub-region, the shield wall extending between adjacent electrical contacts to shield the adjacent electrical contacts from electromagnetic interference, wherein the interposer includes a board substrate and a layer of conductive material bonded to the board substrate, the shield wall being etched from the layer to expose the side surface and define the wall body.
13. The electrical connector assembly of claim 12, further comprising a plurality of the shield walls, each of the shield walls being etched from the layer.
14. An electrical connector assembly comprising:
an interposer having a side surface and an array of electrical contacts that are exposed to an external space along the side surface, the electrical contacts being configured to engage an electronic module mounted over the side surface; and
a shielding matrix including a plurality of shield walls having wall bodies that extend away from the side surface into the external space along the interposer, the wall bodies separating the external space into shielded sub-regions, the shield walls including a conductive material and being electrically coupled to the interposer, wherein at least one electrical contact is located within each shielded sub-region, the shield walls extending between adjacent electrical contacts to shield the respective adjacent electrical contacts from electromagnetic interference.
15. The electrical connector assembly of claim 14, wherein the shield walls are stamped or etched from conductive material.
16. The electrical connector assembly of claim 15, wherein the interposer includes a board substrate and a layer of the conductive material bonded to the board substrate, the shield walls being etched from the layer.
17. The electrical connector assembly of claim 14, wherein the shield walls include a plurality of first shield walls and a plurality of second shield walls, at least some of the first and second shield walls intersecting one another.
18. The electrical connector assembly of claim 14, wherein the shielding matrix forms an interstitial seating plane that is configured to have the electronic module mounted thereon.
19. The electrical connector assembly of claim 14, wherein the shield walls have module edges that are configured to interface with the electronic module and grounding features that are located along the module edge, a ground pathway existing through the grounding feature to the interposer.
20. The electrical connector assembly of claim 14, wherein the side surface is a first side surface and the interposer includes a second side surface that faces in an opposite direction than the first side surface, the shield walls having mounting projections that extend through the interposer and are electrically coupled to corresponding electrical contacts that are exposed along the second side surface.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A processing system comprising:
a clock generator circuit configured to receive a master clock signal and to output a plurality of clock signals, wherein the plurality of clock signals have a first frequency during a built-in self-test (BIST) mode; and
a plurality of shift-capture clock generator circuits, each shift-capture clock generator circuit including a clock gate circuit and a clock divider circuit, wherein:
each of the shift-capture clock generator circuits is configured to receive a corresponding one of the plurality of clock signals, and
at least one of the clock divider circuits changes the first frequency of the one of the plurality of clock signals to a second frequency during the BIST mode.
2. The system of claim 1, further comprising:
a controller configured to generate a plurality of mode select signals and to provide a respective one of the mode select signals to each of the shift-capture clock generator circuits, wherein the mode select signal determines the second frequency.
3. The system of claim 2, wherein a duration of a first half of a clock cycle at the second frequency is approximately the same as a duration of a second half of the clock cycle at the second frequency.
4. The system of claim 1, further comprising:
a controller configured to provide a mode enable signal to each of the shift-capture clock generator circuits, wherein
when the mode enable signal is in a first state, the clock gate circuit outputs the one of the plurality of clock signals as received by the shift-capture clock generator circuit, and
when the mode enable signal is in a second state, the clock gate circuit is disabled and the clock divider circuit outputs the one of the plurality of clock signals at the second frequency.
5. The system of claim 1, further comprising:
a controller configured to provide a test enable signal to each of the shift-capture clock generator circuits, wherein the test enable signal determines whether the shift-capture clock generator circuits are in the test mode.
6. The system of claim 1, further comprising:
the BIST mode includes a shift mode and a capture mode and the frequency of the plurality of clock signals is the second frequency during the shift mode.
7. The system of claim 1, further comprising:
the BIST mode includes a shift mode and a capture mode and frequencies of the plurality of clock signals are different during the capture mode.
8. The system of claim 1, further comprising:
each of the clock gate circuits output the corresponding one of the plurality of clock signals during a normal operation mode.
9. The system of claim 6, further comprising:
a controller coupled to the shift-capture clock generator circuits operable to control the second frequency of at least one test clock signal output by the shift-capture clock generator circuits during a scan test of a circuit under test.
10. The system of claim 1, wherein at least a second one of the clock divider circuits changes the first frequency of the one of the plurality of clock signals to a third frequency during the BIST mode.
11. An integrated circuit processing system comprising:
a plurality of shift-capture clock circuits, each shift-capture clock circuit having a clock gate circuit and a divider clock circuit and being coupled to receive one of a plurality of clock signals at a first frequency during a built-in self-test (BIST) mode, wherein
the clock gate circuits output a respective one of the plurality of clock signals when not in BIST mode,
at least a first of the divider clock circuits outputs a first test clock signal at a second frequency during the BIST mode, and
at least a second of the divider clock circuits outputs a second test clock signal at a third frequency during the BIST mode.
12. The system of claim 11, further comprising:
a controller coupled to the shift-capture clock generator circuits operable to control the second and third frequencies during a scan test of a circuit under test.
13. The system of claim 11, further comprising:
a controller configured to generate a plurality of mode select signals and to provide a respective one of the mode select signals to each of the shift-capture clock generator circuits, wherein a first of the mode select signals determines the second frequency and a second of the mode select signals determines the third frequency.
14. The system of claim 12, wherein a duration of a first half of the first test clock signal at the second frequency is approximately the same as a duration of a second half of the first test clock signal at the second frequency.
15. The system of claim 11, further comprising:
a controller configured to provide a mode enable signal to each of the shift-capture clock generator circuits, wherein the mode enable signal controls whether the first and second of the clock divider circuits output the first and second test clock signals.
16. The system of claim 11, further comprising:
a controller configured to provide a test enable signal to each of the shift-capture clock generator circuits, wherein the test enable signal determines whether the shift-capture clock generator circuits are in the BIST mode.
17. The system of claim 11, further comprising:
the BIST mode includes a shift mode and a capture mode and the second frequency is the same as the third frequency during the shift mode.
18. The system of claim 17, further comprising:
the BIST mode includes a shift mode and a capture mode and the second and third frequencies are different during the capture mode.
19. A method of generating clock signals during a built-in self-test (BIST) mode for an integrated circuit, the method comprising:
receiving a master clock signal in a clock generator circuit;
receiving a control clock signal from a plurality of control clock signals from the clock generator circuit in a shift-capture clock circuit, wherein the plurality of control clock signals have a same frequency during the BIST mode;
when in the BIST mode,
changing the frequency of one of the control clock signals from the same frequency to a second frequency in a divider clock circuit of the shift-capture clock circuit, and
when not in the BIST mode,
outputting the control clock signal using a clock gate circuit in the shift-capture clock circuit.
20. The method of claim 19 further comprising:
generating a mode select signal in a controller of the integrated circuit, wherein the mode select signal is coupled to the divider clock circuit to control the second frequency.