1. A device comprising:
a package component comprising a substrate;
a through-via penetrating through the substrate;
a conductive feature over a first surface of the package component and electrically coupled to the through-via;
a polymer comprising a first portion contacting a sidewall of the substrate, and a second portion overlapped by the package component; and
a first dielectric pattern comprising:
a first portion over and aligned to the polymer; and
a second portion over the substrate and vertically misaligned with the polymer.
2. The device of claim 1, wherein the first dielectric pattern comprises an additional polymer.
3. The device of claim 1, wherein the first dielectric pattern comprises a photo-sensitive material.
4. The device of claim 1 further comprising a device die bonded to the package component, with the device die and the first dielectric pattern being on opposite sides of the package component.
5. The device of claim 1, wherein the polymer forms a first ring encircling the substrate and contacting sidewalls of the substrate, wherein the first dielectric pattern comprises a second ring over and aligned to the first ring, and wherein the first ring and the second ring have outer edges aligned to each other.
6. The device of claim 1 further comprising:
a second dielectric pattern forming a ring covering edge portions of the conductive feature, wherein the first dielectric pattern and the second dielectric pattern are formed of a same dielectric material, coplanar with each other, and disconnected from each other; and
a Under-Bump-Metallurgy (UBM) over and in contact with a center portion of the conductive feature.
7. The device of claim 1, wherein the first dielectric pattern is in physical contact with the polymer.
8. A device comprising:
a first device die comprising:
a semiconductor substrate;
a through-via penetrating through the substrate; and
an interconnect structure over the semiconductor substrate;
a second device die underlying and bonded to the first device die;
a molding compound molding the first device die and the second device die therein, wherein the molding compound encircles the first device die and the second device die, and comprises:
a top surface coplanar with a top surface of the interconnect structure; and
a bottom surface coplanar with a bottom surface of the second device die; and
a polymer layer over the interconnect structure, with bottom surfaces of the polymer layer in contact with top surfaces of the molding compound and the interconnect structure.
9. The device of claim 8, wherein the polymer layer comprises a plurality of discrete portions and a ring portion encircling the plurality of discrete portions, and wherein the plurality of discrete portions and the ring portion are physically separated from each other.
10. The device of claim 9, wherein the ring portion has outer edges aligned to edges of the molding compound.
11. The device of claim 9 further comprising:
a plurality of Under-Bump-Metallurgies (UBMs) extending into the discrete portions; and
a plurality of solder regions over and contacting the plurality of UBMs.
12. The device of claim 8, wherein the polymer layer is formed of a photo-sensitive material.
13. The device of claim 8, wherein the molding compound comprises an additional portion overlapped by the first device die.
14. A device comprising:
a package component comprising a substrate, wherein the substrate comprises a front surface, and a back surface over the front surface;
a through-via penetrating through the substrate;
a die underlying and bonded to a front side of the package component;
a polymer encircling, and in physical contact with, sidewalls of the substrate and sidewalls of the die; and
an insulation layer over the substrate, wherein the insulation layer comprises a bottom surface contacting the back surface of the substrate, and a top surface substantially coplanar with a top surface of the polymer, and wherein the through-via penetrates through the insulation layer.
15. The device of claim 14, wherein sidewalls of the insulation layer are in physical contact with sidewalls of the polymer.
16. The device of claim 14, wherein the polymer comprises an outer sidewall forming a ring, wherein the outer sidewall comprises a first portion level with the substrate, and a second portion level with the die, and the first portion and the second portion of the outer sidewall are continuous and vertically aligned with each other.
17. The device of claim 14 further comprising:
a conductive feature over the back surface of the substrate and electrically coupled to the through-via;
a first dielectric pattern forming a ring covering edge portions of the conductive feature;
a Under-Bump-Metallurgy (UBM) over and in contact with a center portion of the conductive feature; and
a second dielectric pattern over and aligned to the polymer, wherein the first dielectric pattern and the second dielectric pattern are separated from each other, and wherein the first and the second dielectric patterns are formed of a same dielectric material.
18. The device of claim 17, wherein the first and the second dielectric patterns comprise a polymer.
19. The device of claim 17, wherein the first and the second dielectric patterns comprise a photo sensitive material.
20. The device of claim 17, wherein the second dielectric pattern forms a ring, with an outer edge of the ring aligned with respective outer edges of the polymer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A switch device comprising:
a first depletion-mode transistor configured to pass an analog signal between a first node and a second node in a first state and to isolate the first node from the second node in a second state;
a control circuit coupled to a control node of the first depletion-mode transistor, the control circuit configured to isolate the control node from a first supply input in the first state and to couple the control node to the first supply input in the second state; and
a tracking circuit configured to couple the control node of the first depletion-mode transistor to the first node during the first state and to isolate the control node of the first depletion-mode transistor from the first node in the second state.
2. The switch device of claim 1, wherein the control circuit includes:
an inverter having an input coupled to the first supply input; and
an enhancement-mode transistor configured to receive an output of the inverter and to control the control node using the output of the inverter.
3. The switch device of claim 2, including a first voltage discriminator coupled to the first node;
wherein a first supply input of the inverter is configured to be coupled to ground;
wherein a second supply input of the inverter is configured to be coupled to an output of the first voltage discriminator; and
wherein the first voltage discriminator is configured to receive a plurality voltage levels and to provide, at the output of the first voltage discriminator, a voltage level substantially equal to the lowest of the plurality voltage levels.
4. The switch device of claim 3, wherein the plurality of voltage levels includes a voltage level of the first or second supply input.
5. The switch device of claim 3, wherein the plurality of voltage levels includes a voltage level of the first node.
6. The switch device of claim 3, including a second voltage discriminator coupled to the second node and the output of the first discriminator;
wherein the second voltage discriminator is configured to receive a second plurality voltage levels and to provide, at an output of the second voltage discriminator, a voltage level substantially equal to the lowest voltage level of the second plurality voltage levels; and
wherein the second plurality of voltage levels includes a voltage level of the first or second supply input and a voltage level of the second node.
7. The switch device of claim 1, wherein the tracking circuit includes a second depletion-mode transistor coupled to the control node of the first depletion-mode transistor, the second depletion-mode transistor configured to couple the control node of the first depletion-mode transistor to the first node in the first state and to isolate the control node of the first depletion-mode transistor from the first node in the second state.
8. The switch device of claim 7, further including a second supply input coupled to a control node of the second depletion-mode transistor;
wherein the first supply input and the second supply input are configured to receive a first voltage in the first state;
wherein the first supply input is configured to receive a second voltage in the second state;
wherein the second supply input is configured to receive a third voltage in the second state; and
wherein the third voltage is lower than the second voltage and the second voltage is lower than the first voltage.
9. The switch device of claim 1, wherein the tracking circuit includes a first tracking circuit configured to couple the first node to the control node of the first depletion-mode transistor in the first state and to isolate the first node from the control node of the first depletion-mode device in the second state;
wherein the first tracking circuit includes a PMOS transistor coupled in parallel with an NMOS transistor;
wherein a control node of the NMOS transistor is coupled to the first supply; and
wherein a control node of the PMOS transistor is coupled to the first node when a voltage level of the first node is lower than ground level in the first state.
10. The switch device of claim 9, wherein the tracking circuit includes a second tracking circuit configured to couple the second node to the control node of the first depletion-mode transistor in the first state, and to isolate the second node from the control node of the first depletion-mode device in the second state;
wherein the first tracking circuit includes a PMOS transistor coupled in parallel with an NMOS transistor;
wherein a control node of the NMOS transistor is coupled to the first supply; and
wherein a control node of the PMOS transistor is coupled to the first node when a voltage level of the first node is lower than ground level in the first state.
11. The switch device of claim 10, including a third voltage discriminator configured to provide an output to control the PMOS transistor of the first tracking circuit and the PMOS transistor of the second tracking circuit.
12. The switch device of claim 1, wherein a back gate of the first depletion-mode transistor is coupled to the control node of the first depletion-mode transistor.
13. A method comprising:
passing an analog signal between a first node and a second node using a first depletion-mode transistor in a first state;
isolating the first node from the second node in using the first depletion-mode transistor in a second state;
isolating a control node of the first depletion-mode transistor from a first supply input in the first state using a control circuit;
coupling the control node of the first depletion-mode transistor to the first supply input in the second state using the control circuit;
coupling the control node of the first depletion-mode transistor to the first node in the first state using a tracking circuit; and
isolating the control node of the first depletion-mode transistor from the first node in the second state using the tracking circuit.
14. The method of claim 13, wherein coupling the control node of the first depletion-mode transistor to the first node includes coupling the control node of the first depletion-mode transistor to the first node in the first state using a second depletion-mode transistor.
15. The method of claim 14, wherein isolating the first node from the second node includes coupling a negative voltage to the first supply input.
16. The method of claim 15, wherein isolating the first node from the second node includes coupling a second negative voltage to a control node of the second depletion-mode transistor.
17. The method of claim 13, wherein isolating a control node of the first depletion-mode transistor from a first supply input includes coupling a control node of an output transistor of the control node to a supply rail using an inverter, wherein the output transistor is coupled to the first supply input, the control node of the first depletion-mode transistor and an output of the inverter.
18. The method of claim 17, wherein coupling a control node of an output transistor of the control node to a supply rail using an inverter includes providing at the supply rail a lowest voltage using a voltage discriminator of voltages present at the first supply input, the first node and the second node.
19. The method of claim 13, wherein coupling the control node of the first depletion-mode transistor to the first node includes
coupling the control node of an NMOS transistor of a tracking circuit to the first supply input; and
coupling a control node of a PMOS transistor of the tracking circuit to the first node when a voltage level of the first node is lower than ground level in the first state.
20. The method of claim 13, including coupling a back gate of the first depletion-mode transistor to the control node of the first depletion-mode transistor.