1. An integrated circuit comprising:
an interconnecting copper metallization;
a first insulating overcoat layer on the metallization;
a second insulating overcoat layer on the first overcoat layer, the second overcoat layer consisting of homogeneous silicon dioxide;
portions of the copper metallization exposed in a window through the first and second overcoat layers, the window having a rim;
a patterned conductive barrier layer on the exposed copper metallization, the window rim, and a portion of the second overcoat layer adjacent to the window rim;
a layer of bondable metal covering the patterned barrier layer, the bondable metal layer having an edge; and
a third insulating overcoat layer on the second overcoat layer and the edge of the bondable metal layer, the third insulating layer consisting of a homogeneous silicon nitride compound and forming a ledge of more than 500 nm height over the bondable metal layer.
2. The circuit according to claim 1 wherein the first insulating overcoat layer is made of silicon nitride and has a thickness between about 30 to 50 nm.
3. The circuit according to claim 1 wherein the second overcoat has a thickness in the range from about 200 to 1200 nm.
4. The circuit according to claim 1 wherein said barrier layer includes tantalum nitride and has a thickness in the range from about 20 to 30 nm.
5. The circuit according to claim 1 wherein the bondable metal layer includes aluminum or aluminum alloy and has a thickness in the range from about 400 to 1400 nm.
6. The circuit according to claim 1 further including a ball bond attached to the bondable metal layer.
7. The circuit according to claim 1 wherein the barrier and bondable metal layers overlap over the surrounding second overcoat layer for a length of about 100 to 300 nm.
8. The circuit according to claim 1 wherein the ledge of the third overcoat layer overlaps over the edge of the bondable metal layer for a length of about 100 to 300 nm.
9. A method for fabricating a metal contact structure on a semiconductor wafer comprising the steps of:
providing a semiconductor wafer having an interconnecting copper metallization;
planarizing the wafer surface to expose at least portions of the copper metallization;
depositing a first insulating overcoat layer over the planar wafer surface;
depositing a second insulating overcoat layer on the first overcoat layer, the second overcoat layer consisting of homogeneous silicon dioxide;
opening a window through the first and second overcoat layers to expose portions of the copper metallization, the window having a rim;
depositing a conductive barrier metal layer on the exposed copper metallization, the window rim, and the second overcoat layer;
depositing on the barrier layer a layer of bondable metal in a thickness suitable for wire ball bonding;
patterning the bondable and the barrier layers to retain only the portions inside the window, over the rim, and portions of the second overcoat adjacent to the window rim, whereby the bondable metal layer obtains an edge;
depositing a third insulating overcoat layer on the second overcoat layer and the bondable metal layer, the third overcoat layer consisting of a homogeneous silicon nitride compound and having a thickness of more than 500 nm; and
selectively removing the third overcoat layer from the bondable metal layer so that the metal edge remains covered by the overcoat and an overcoat ledge of more than 500 nm height is formed over the edge of the bondable metal.
10. The method according to claim 9 wherein the first layer of insulating overcoat is made of silicon nitride and has a thickness in the range from about 30 to 50 nm.
11. The method according to claim 9 wherein the silicon dioxide layer has a thickness between about 200 and 1200 nm.
12. The method according to claim 9 wherein the barrier metal layer includes tantalum nitride in the thickness range from about 20 to 30 nm.
13. The method according to claim 9 wherein the bondable metal layer includes aluminum or aluminum alloy in the thickness range from about 400 to 1400 nm.
14. The method according to claim 9 further including, after selectively removing the third overcoat layer, the steps of singulating the wafer into discrete chips, attaching a selected chip onto a leadframe, and attaching a wire ball bond to the bondable metal layer of the chip.
15. The method according to claim 14 further including, after the step of attaching a ball bond, the step of molding the chip surface including the bonded metal contact structure in plastic encapsulation compound.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A handling method for voltage faults applicable for using in a computer system, the handling method comprising:
acquiring a signal of voltage fault;
according to the signal of voltage fault and by looking up at tables, acquiring an operating status of the computer system corresponding to the signal of voltage fault, and generating a control signal according to the operating status; and
restarting the computer system according to the control signal.
2. The handling method for voltage faults as claimed in claim 1, further comprising:
determining if a restarting of the computer system is successful;
if the restarting of the computer system being determined to be unsuccessful, determining if a number of times of restarting the computer system being over a preset number;
if determining that the number of times being over the preset number, then turning off the computer system; and
if determining that the number of times not being over the preset number, then returning back to the step of determining if the restarting of the computer system is successful.
3. The handling method for voltage faults as claimed in claim 1, further comprising:
detecting if the signal of voltage fault being present;
if the signal of voltage fault not being detected, returning back to the step of detecting if the signal of voltage fault being present; and
if the signal of voltage fault being detected, proceeding with the step of acquiring the signal of voltage fault.
4. The handling method for voltage faults as claimed in claim 1, wherein the operating status includes the computer system before or after an idle status, a status of a power supply unit, a type of voltage as well as the computer system under a stage of startup or a stage of runtime.
5. The handling method for voltage faults as claimed in claim 1, wherein the control signal includes a delay time and a number of times of restarting the computer system.
6. A handling device for voltage faults applicable for using in a computer system, the handling device comprising:
a detecting unit used to detect if a fault occurred in a voltage of the computer system in order to generate a signal of voltage fault;
a comparison unit coupled to the detecting unit to receive the signal of voltage fault, and by looking up at tables, an operating status of the computer system corresponding to the signal of voltage fault being acquired, and a control signal being generated according to the operating status; and
a control unit coupled to the comparison unit to receive the control signal and control a restarting of the computer system according to the control signal.
7. The handling device for voltage faults as claimed in claim 6, wherein the control unit further determines if the restarting of the computer system has succeeded, if the restarting of the computer system is determined to be unsuccessful, the control unit determines if a number of times of restarting the computer system is over a preset number, if it is determined that the number of times is over the preset number, then the control unit controls the computer system to be turned off, if it is determined that the number of times is not over the preset number, the control unit determines if the restarting of the computer system has succeeded again, until the computer system is restarted successfully or until the computer system is turned off.
8. The handling device for voltage faults as claimed in claim 6, wherein the operating status includes the computer system before or after an idle status, a status of a power supply unit, a type of voltage as well as the computer system under a stage of startup or a stage of runtime.
9. The handling device for voltage faults as claimed in claim 6, wherein the control signal includes a delay time and a number of times of restarting the computer system.