1. A chip comprising:
an inputoutput (IO) controller having:
a traffic monitor to monitor the traffic;
an interface to storage device; and
logic to place a processor in a non-snoopable idle state while the interface is enabled for traffic between the interface and the storage device and the traffic ceases for a period of time shorter than a seek time associated with the storage device.
2. The chip of claim 1, wherein the IO controller is to disable the traffic monitor if a system containing the storage interface is operating on alternating current (AC) power.
3. The chip of claim 1, wherein the logic is to remove the processor from the non-snoopable idle state if a data transfer is ready to occur between the interface and the storage device.
4. The chip of claim 3, wherein the logic is to delay the data transfer based on an exit latency associated with the non-snoopable idle state.
5. The chip of claim 1, wherein the interface includes at least one of an integrated device electronics (IDE) controller and a serial advanced technology attachment (SATA) host bus adapter.
6. A method comprising:
placing a processor in a non-snoopable idle state while a storage interface associated with the processor is enabled for traffic between the interface and a storage device and the traffic ceases for a period of time shorter than a seek time associated with the storage device.
7. The method of claim 6, further including disabling the monitoring if a system containing the storage interface is operating on alternating current (AC) power.
8. The method of claim 6, further including removing the processor from the non-snoopable idle state if a data transfer is ready to occur between the storage interface and a storage device.
9. The method of claim 8, further including delaying the data transfer based on an exit latency associated with the non-snoopable idle state.
10. A system comprising:
a first chip including a processor with a memory controller; and
a second chip with an inputoutput (IO) controller coupled to the processor, the IO controller including;
a traffic monitor to monitor the traffic;
an interface to a storage device; and
logic to place a processor in a non-snoopable idle state while the interface is enabled for traffic between the interface and the storage device and the traffic ceases for a period of time shorter than a seek time associated with the storage device.
11. The system of claim 10, wherein the IO controller is to disable the traffic monitor if the system is operating on alternating current (AC) power.
12. The system of claim 10, wherein the logic is to remove the processor from the non-snoopable idle state if a data transfer is ready to occur between the storage interface and a storage device.
13. The system of claim 12, wherein the logic is to delay the data transfer based on an exit latency associated with the non-snoopable idle state.
14. The system of claim 10, wherein the interface includes at least one of an integrated device electronics (IDE) controller and a serial advanced technology attachment (SATA) host bus adapter.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A method of manufacturing a vibrating gyroscope including a vibrator and an enclosure having a support for supporting the vibrator formed thereon, the method comprising the steps of:
integrally forming a positioning member with the enclosure, said positioning member being used to determine a position of the vibrator with respect to the enclosure; and
supporting the vibrator by the support while the vibrator is positioned with respect to the enclosure by the positioning member.
2. A method of manufacturing a vibrating gyroscope according to claim 1, further comprising the step of removing the positioning member from the enclosure after the step of supporting the vibrator by the support.
3. A method of manufacturing a vibrating gyroscope according to either claim 1 or claim 2, wherein the vibrator is supported by the support through a supporting member.