We claim:
1. A method for producing trenches for manufacturing storage capacitors in DRAM cell configurations, which comprises:
forming a first mask layer having a thickness between 100 nm and 250 nm from an SiO2 layer;
forming a second mask layer having a thickness greater than 850 nm from a layer selected from the group consisting of a polysilicon layer and a crystalline silicon layer;
providing the second mask layer underlying the first mask layer;
placing the first mask layer and the underlying second mask layer on a wafer that forms a semiconductor substrate;
providing a resist mask having a hole pattern and placing the resist mask on the first mask layer;
performing a first etching process to selectively etch the first mask layer with respect to the resist mask and to structure recesses in the first mask layer in correspondence with the hole pattern of the resist mask; and
subsequently, performing a second etching process to selectively etch the second mask layer with respect to the first mask layer and to structure recesses in the second mask layer through the recesses of the first mask layer.
2. The method according to claim 1, which comprises covering a wafer margin while the recesses in the first mask layer are structured.
3. The method according to claim 2, which comprises using a collar to cover the wafer margin.
4. The method according to claim 1, which comprises removing the resist mask prior to structuring the recesses in the second mask layer.
5. The method according to claim 1, wherein the first etching process is a plasma etching process and the second etching process is a plasma etching process.
6. The method according to claim 5, which comprises using a high-density plasma source to perform the first etching process.
7. The method according to claim 5, which comprises using a method selected from the group consisting of an RIE method and an MERIE method to perform the second etching process.
8. The method according to claim 1 which comprises providing the resist mask with a resist layer having a thickness from 500 nm to 600 nm and with an underlying antireflective layer having a thickness from 50 nm to 60 nm.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An electromagnetic interference (EMI) shielded semiconductor package comprising:
a semiconductor package; and
an EMI shield layer on at least a part of a surface of the EMI shielded semiconductor package,
wherein the EMI shield layer includes,
a matrix layer;
a metal layer on the matrix layer; and
a first seed particle in an interface between the matrix layer and the metal layer.
2. The EMI shielded semiconductor package of claim 1, wherein the first seed particle includes a core particle and a surface modifying layer coated on at least a part of the core particle.
3. The EMI shielded semiconductor package of claim 2, wherein the surface modifying layer is between the core particle and the matrix layer.
4. The EMI shielded semiconductor package of claim 2, wherein the surface modifying layer includes at least one of a polymer containing a thiol (\u2014SH) group, a silane-based compound containing an alkoxy group with 1 to 10 carbon atoms, acetylacetone and a mixture thereof.
5. The EMI shielded semiconductor package of claim 2, wherein the core particle is at least one of a metal and metal oxide.
6. The EMI shielded semiconductor package of claim 2, further comprising:
a second seed particle in the matrix layer.
7. The EMI shielded semiconductor package of claim 6, wherein the second seed particle includes a core particle and a surface modifying layer and the surface modifying layer of the second seed particle substantially coats the entire surface of the core particle of the second seed particle.
8. The EMI shielded semiconductor package of claim 1, wherein a diameter of the first seed particle is in a range between 2 and 80 \u03bcm.
9. The EMI shielded semiconductor package of claim 1, wherein the semiconductor package includes a top surface and a side surface and the EMI shield layer is on at least a part of the top surface and the side surface.
10. An electromagnetic interference (EMI) shielded substrate module comprising:
a substrate;
a semiconductor package on the substrate; and
an EMI shield layer on at least a part of surfaces of the substrate and the semiconductor package,
wherein the EMI shield layer includes,
a matrix layer;
a metal layer on the matrix layer; and
a first seed particle in an interface between the matrix layer and the metal layer.
11. The EMI shielded substrate module of claim 10, wherein the substrate includes a ground electrode and the metal layer is electrically connected to the ground electrode.
12. The EMI shielded substrate module of claim 11, wherein the matrix layer is configured to expose at least one of at least a portion of the ground electrode and at least a portion of a wiring pattern that is electrically connected to the ground electrode, and the metal layer contacts at least one of the at least a portion of the ground electrode and the at least a portion of a wiring pattern that is electrically connected to the ground electrode that is exposed by the matrix layer.
13. The EMI shielded substrate module of claim 12, wherein the matrix layer includes a hole penetrating the matrix layer and at least one of the at least a portion of the ground electrode and the at least a portion of a wiring pattern that is electrically connected to the ground electrode is exposed through the hole.
14. The EMI shielded substrate module of claim 12, wherein the metal layer extends to an external wall of the matrix layer to be electrically connected to at least one of the ground electrode and the wiring pattern electrically connected to the ground electrode.
15. The EMI shielded substrate module of claim 10, wherein a plurality of semiconductor packages are on the substrate.
16. An electromagnetic interference (EMI) shielded semiconductor package comprising:
a matrix layer including a plurality of seed particles; and
a metal layer on the matrix layer, an interface between the matrix layer and the metal layer including at least one of the plurality of seed particles.
17. The EMI shielded semiconductor package of claim 16, wherein the at least one of the plurality of seed particles includes at least one core particle and at least one surface modifying layer coated on at least a part of the core particle.
18. The EMI shielded semiconductor package of claim 17, wherein the at least one surface modifying layer is between the at least one core particle and the matrix layer.
19. The EMI shielded semiconductor package of claim 17, wherein the at least one surface modifying layer includes at least one of a polymer containing a thiol (\u2014SH) group, a silane-based compound containing an alkoxy group with 1 to 10 carbon atoms, acetylacetone and a mixture thereof.