1. A check chip which is mounted on a measuring device employing an exclusively used sensor, and checks operations of the measuring device itself, wherein
the check chip is provided thereon with at least one structural characterizing portion which makes a user of the measuring device recognize differences from a correction chip for correcting errors that occur with lot changes in the exclusively used sensor.
2. The check chip of claim 1, wherein
the structural characterizing portion has a shape, such as a convex shape, which can be recognized by the user from the touch, and is provided in a location by which the user is considered to pick up the check chip.
3. The check chip of claim 1 or claim 2, wherein a difference between the check chip and the correction chip resides in the size of the structural characterizing portion, when the correction chip has the structural characterizing portion.
4. The check chip of claim 3, wherein
the size of the structural characterizing portion provided on the check chip is larger than that of the structural characterizing portion provided on the correction chip.
5. The check chip of claim 3, wherein
the size of the structural characterizing portion provided on the check chip is smaller than that of the structural characterizing portion provided on the correction chip.
6. The check chip of any of claims 1 to 5, wherein
the check chip is provided with the structural characterizing portion on the both sides of the check chip.
7. The check chip of any of claims 1 to 6, wherein a difference between the check chip and the correction chip resides in the number of the structural characterizing portions.
8. The check chip of claim 7, wherein
the number of the structural characterizing portions provided on the check chip is larger than that of the structural characterizing portions provided on the correction chip.
9. The check chip of claim 7, wherein
the number of the structural characterizing portions provided on the check chip is smaller than that of the structural characterizing portions provided on the correction chip.
10. The check chip of claim 8, wherein
structural characterizing portion on an attention attracting character printed on an upside of the check chip, among plural structural characterizing portions provided on the check chip, has optical penetrability.
11. The check chip of any of claims 1 to 10, wherein a difference between the check chip and the correction chip reside in the shape of the structural characterizing portion.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A bit-and-one-half analog to digital converter, comprising:
a switched capacitor circuit, including an opamp, that receives an analog input voltage and generates a residual analog output voltage, wherein said switched capacitor circuit samples said analog input voltage during a sampling phase and generates said residual analog output voltage during an integration phase;
a comparator that generates a digital output based on said analog output voltage generated by said switched capacitor circuit; and
a current source that communicates with said opamp and is operable to supply a first bias current to said opamp during said sampling phase and a second bias current that is greater than said first bias current to said opamp during said integration phase.
2. The bit-and-one-half analog to digital converter of claim 1 wherein said switched capacitor circuit includes a capacitor that stores said sampled analog input voltage during said sampling phase.
3. The bit-and-one-half analog to digital converter of claim 2 wherein said sampled analog input voltage stored by said capacitor is integrated by said opamp during said integration phase to generate said residual analog output voltage.
4. The bit-and-one-half analog to digital converter of claim 1 wherein said first bias current is a fractional portion of said second bias current.
5. The bit-and-one-half analog to digital converter of claim 1 wherein said first bias current is zero.
6. A multi-stage pipelined analog to digital converter, comprising:
a plurality of bit-and-one-half converter stages arranged in series, each converter stage receiving an analog input voltage and generating a residual analog output voltage, wherein each converter stage further comprises:
a switched capacitor circuit, including an opamp, that receives said analog input voltage and generates said residual analog output voltage, wherein said switched capacitor circuit samples said analog input voltage during a sampling phase and generates said residual analog output voltage during an integration phase;
a comparator that generates a digital stage output based on said residual analog output voltage generated by said switched capacitor circuit;
a current source that communicates with said opamp and is operable to supply a first bias current to said opamp during said sampling phase and a second bias current that is greater than said first bias current to said operation amplifier during said integration phase; and
a correction circuit that accepts said digital stage output from each of said converter stages and generates a corresponding digital output.
7. The multi-stage pipelined analog to digital converter of claim 6 wherein said switched capacitor circuit includes a capacitor that stores said sampled analog input voltage during said sampling phase.
8. The multi-stage pipelined analog to digital converter of claim 7 wherein said sampled analog input voltage stored by said capacitor is integrated by said opamp during said integration phase to generate said residual analog output voltage.
9. The multi-stage pipelined analog to digital converter of claim 6 wherein said first bias current is a fractional portion of said second bias current.
10. The multi-stage pipelined analog to digital converter of claim 6 wherein said first bias current is zero.
11. A bit-and-one-half analog to digital converter, comprising:
switched capacitor means, including integrating means for integrating signals input thereto, for receiving an analog input voltage and for generating a residual analog output voltage, wherein said switched capacitor means samples said analog input voltage during a sampling phase and generates said residual analog output voltage during an integration phase;
comparing means for generating a digital output based on said analog output voltage generated by said switched capacitor means; and
current means that communicates with said integrating means for supplying a first bias current to said integrating means during said sampling phase and a second bias current that is greater than said first bias current to said integrating means during said integration phase.
12. The bit-and-one-half analog to digital converter of claim 11 wherein said switched capacitor means includes a capacitor that stores said sampled analog input voltage during said sampling phase.
13. The bit-and-one-half analog to digital converter of claim 12 wherein said sampled analog input voltage stored by said capacitor is integrated by said integrating means during said integration phase to generate said residual analog output voltage.
14. The bit-and-one-half analog to digital converter of claim 11 wherein said first bias current is a fractional portion of said second bias current.
15. The bit-and-one-half analog to digital converter of claim 11 wherein said first bias current is zero.
16. A multi-stage pipelined analog to digital converter, comprising:
a plurality of bit-and-one-half converter stages arranged in series, each converter stage receiving an analog input voltage and generating a residual analog output voltage, wherein each converter stage further comprises:
switched capacitor means, including an integrating means for integrating signals input thereto, for receiving said analog input voltage and for generating said residual analog output voltage, wherein said switched capacitor means samples said analog input voltage during a sampling phase and generates said residual analog output voltage during an integration phase;
comparing means for generating a digital stage output based on said residual analog output voltage generated by said switched capacitor means;
current means that communicates with said integrating means for supplying a first bias current to said integrating means during said sampling phase and a second bias current that is greater than said first bias current to said operation amplifier during said integration phase; and
correction means for accepting said digital stage output from each of said converter stages and for generating a corresponding digital output.
17. The multi-stage pipelined analog to digital converter of claim 16 wherein said switched capacitor means includes a capacitor that stores said sampled analog input voltage during said sampling phase.
18. The multi-stage pipelined analog to digital converter of claim 17 wherein said sampled analog input voltage stored by said capacitor is integrated by said integrating means during said integration phase to generate said residual analog output voltage.
19. The multi-stage pipelined analog to digital converter of claim 16 wherein said first bias current is a fractional portion of said second bias current.
20. The multi-stage pipelined analog to digital converter of claim 16 wherein said first bias current is zero.
21. A method of operating a bit-and-one-half analog to digital converter, comprising:
sampling an analog input voltage during a sampling phase;
generating a residual analog output voltage during an integration phase using an opamp;
generating a digital output based on said residual analog output voltage; and
supplying a first bias current to said opamp during said sampling phase and a second bias current that is greater than said first bias current to said opamp during said integration phase.
22. The method of claim 21 further comprising using a capacitor to store said sampled analog input voltage during said sampling phase.
23. The method of claim 22 further comprising integrating said sampled analog input voltage stored by said capacitor using said opamp during said integration phase to generate said residual analog output voltage.
24. The method of claim 21 wherein said first bias current is a fractional portion of said second bias current.
25. The method of claim 21 wherein said first bias current is zero.