1. A semiconductor device comprising:
a semiconductor substrate having a first surface and a second surface facing the first surface;
a plurality of first semiconductor layers of a first conductive type provided in the semiconductor substrate of the second surface side, the first semiconductor layers extending in a first direction, the first semiconductor layers arranged in a second direction orthogonal to the first direction, each of the first semiconductor layers surrounded by a gate layer, a gate insulating film interposed between each of the first semiconductor layers and the gate layer;
a plurality of second semiconductor layers of the first conductive type provided between the first semiconductor layers adjacent to each other in the second direction, the second semiconductor layers having a depth smaller than a depth of the first semiconductor layers in a direction toward the first surface from the second surface;
a plurality of third semiconductor layers of the first conductive type provided in the semiconductor substrate of the second surface side, each of the third semiconductor layers arranged at ends of the first direction of each of the first semiconductor layers, each of the third semiconductor layers surrounded by the gate layer, the gate insulating film interposed between each of the third semiconductor layers and the gate layer, a depth of the third semiconductor layers being substantially equal to the depth of the first semiconductor layers in the direction toward the first surface from the second surface;
a fourth semiconductor layer of a second conductive type provided in the semiconductor substrate at the second surface side of the second semiconductor layers;
a sixth semiconductor layer of the first conductive type provided in the semiconductor substrate at the first surface side of the first semiconductor layers;
a seventh semiconductor layer of the second conductive type provided between the first, second, and third semiconductor layers and the sixth semiconductor layer;
an emitter electrode electrically connected to the third and fourth semiconductor layers; and
a collector electrode electrically connected to the sixth semiconductor layer.
2. The semiconductor device according to claim 1, wherein an end of the gate layer in the semiconductor substrate in the first direction has a curved shape.
3. The semiconductor device according to claim 1, further comprising:
an eighth semiconductor layer of the first conductive type provided in the semiconductor substrate of the second surface side, the eighth semiconductor layer arranged at ends of the second semiconductor layers in the first direction, the eighth semiconductor layer having a depth equal to that of the first semiconductor layers in a direction toward the first surface from the second surface,
wherein the emitter electrode is electrically connected to the eighth semiconductor layer.
4. The semiconductor device according to claim 1, further comprising:
a tenth semiconductor layer of the first conductive type provided in the semiconductor substrate of the second surface side, the tenth semiconductor layer arranged at the ends of the first semiconductor layers in the second direction with the gate insulating film interposed between the first semiconductor layers and the tenth semiconductor layer, the tenth semiconductor layer extending in the first direction, the tenth semiconductor layer having a depth substantially equal to that of the first semiconductor layers in a direction toward the first surface from the second surface,
wherein the emitter electrode is electrically connected to the tenth semiconductor layer.
5. The semiconductor device according to claim 1, further comprising:
a plurality of fifth semiconductor layers provided between the third semiconductor layers and the emitter electrode, the fifth semiconductor layers contacting the emitter electrode, the fifth semiconductor layers having an impurity concentration of the first conductive type higher than that of the third semiconductor layers.
6. The semiconductor device according to claim 3, further comprising:
a ninth semiconductor layer provided between the eighth semiconductor layer and the emitter electrode, the ninth semiconductor layer contacting the emitter electrode, the ninth semiconductor layer having an impurity concentration of the first conductive type higher than that of the eighth semiconductor layer.
7. The semiconductor device according to claim 1, further comprising:
a gate extraction layer connected to an end of the gate layer in the first direction, the gate extraction layer provided above the semiconductor substrate of the second surface side.
8. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of single-crystalline silicon.
9. The semiconductor device according to claim 1, wherein the first conductive type is a p type and the second conductive type is an n type.
10. The semiconductor device according to claim 1, wherein the gate insulating film is a silicon oxide film.
11. A semiconductor device comprising:
a semiconductor substrate having a first surface and a second surface facing the first surface;
a plurality of first semiconductor layers of a first conductive type provided in the semiconductor substrate of the second surface side, the first semiconductor layers extending in a first direction, the first semiconductor layers arranged in a second direction orthogonal to the first direction, each of the first semiconductor layers surrounded by a gate layer, a gate insulating film interposed between each of the first semiconductor layers and the gate layer;
a plurality of second semiconductor layers of the first conductive type provided between the first semiconductor layers adjacent to each other in the second direction, the second semiconductor layers having a depth smaller than a depth of the first semiconductor layers in a direction toward the first surface from the second surface;
a third semiconductor layer of the first conductive type provided in the semiconductor substrate of the second surface side, the third semiconductor layer arranged at ends of the first direction of the first semiconductor layers, the third semiconductor layer provided with the gate layer interposed between the first semiconductor layers and the third semiconductor layer, the third semiconductor layer having a depth substantially equal to the depth of the first semiconductor layers in the direction toward the first surface from the second surface;
an extracting gate layer extending from an end of the first direction of the gate layer to an inner portion of the third semiconductor layer in the first direction;
a fourth semiconductor layer of a second conductive type provided in the semiconductor substrate at the second surface side of the second semiconductor layers;
a sixth semiconductor layer of the first conductive type provided in the semiconductor substrate at the first surface side of the first semiconductor layers;
a seventh semiconductor layer of the second conductive type provided between the first, second, and third semiconductor layers and the sixth semiconductor layer;
an emitter electrode electrically connected to the third and fourth semiconductor layers; and
a collector electrode electrically connected to the sixth semiconductor layer.
12. The semiconductor device according to claim 11, further comprising:
a fifth semiconductor layer provided between the third semiconductor layer and the emitter electrode, the fifth semiconductor layer contacting the emitter electrode, the fifth semiconductor layer having an impurity concentration of the first conductive type higher than that of the third semiconductor layer.
13. The semiconductor device according to claim 11, further comprising:
a gate extraction layer connected to an end of the gate layer in the first direction, the gate extraction layer provided above the semiconductor substrate of the second surface side.
14. The semiconductor device according to claim 11, wherein the semiconductor substrate is made of single-crystalline silicon.
15. The semiconductor device according to claim 11, wherein the first conductive type is a p type and the second conductive type is an n type.
16. The semiconductor device according to claim 11, wherein the gate insulating film is a silicon oxide film.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. Nonwoven containing FR-treated inherent FR cellulosic fiber.
2. The nonwoven of claim 1, further comprising one or more optional fibers which are different from said FR-treated inherent FR cellulosic fiber.
3. The nonwoven of claim 1, further comprising a low-melt binder fiber for thermal bonding of the nonwoven
4. The nonwoven of claim 1, wherein fibers are mechanically bonded together.
5. The nonwoven of claim 1, fibers are chemically bonded together.
6. The nonwoven of claim 1 wherein said nonwoven has a basis weight ranging from 0.1\u02dc5.0 ozft2 .
7. A method of making a nonwoven fire barrier with improved physical performance, comprising the steps of:
forming a nonwoven which includes at least one untreated inherent FR cellulosic fiber;
applying one or more fire retardant chemicals to the nonwoven;
and drying the nonwoven.
8. The method of claim 7 further comprising the step of passing the nonwoven through padder rolls prior to said drying step.
9. The method of claim 7 wherein said step of applying is performed by padding, spraying, kiss roll application, foam application, blade application, or vacuum extraction application.
10. The nonwoven of claim 7 wherein said nonwoven has a basis weight ranging from 0.1\u02dc5.0 ozft2 .