1. An annular array of aerofoils for a gas turbine engine, the array defining a cooling arrangement, the arrangement comprising a junction gap between two overlapping platforms of adjacent aerofoils and a damper radially inwardly of the junction gap, a damper surface and a platform surface arranged to have a coolant flow passing between them in use, the arrangement characterised in that the junction gap is at an angle relative to a radial line to angularly present a coolant flow in use adjacent to an exit of the junction gap.
2. An annular array of aerofoils as claimed in claim 1 wherein the junction gap is angled \xf8 between 30 and 75 degrees.
3. An annular array of aerofoils as claimed in claim 1 wherein the junction gap is angled \xf8 is approximately 60 degrees.
4. An annular array of aerofoils as claimed in claim 1 wherein the angle of the junction gap varies along the length of the platforms.
5. An annular array of aerofoils as claimed in claim 1 wherein the damper surface has a ridge with surfaces either side and the angle of the junction gap is substantially aligned with one of the surfaces.
6. An annular array of aerofoils as claimed in claim 1 wherein the junction gap forms a slot which is continuous along the length of the platforms.
7. An annular array of aerofoils as claimed in claim 6 wherein the ridge is directly radially inward the slot.
8. An annular array of aerofoils as claimed in claim 5 thereon wherein the surfaces are arranged such that respective coolant flows over both surfaces merge at the ridge to form the coolant flow presented adjacent to the exit of the junction gap.
9. An annular array of aerofoils as claimed in claim 6 wherein the slot has an exit configured to present the coolant flow adjacent to the junction gap.
10. An annular array of aerofoils as claimed in claim 9 wherein the exit is arranged to present the coolant flow at a substantially consistent angle to gas flows over the platforms in use.
11. An annular array of aerofoils as claimed in claim 9 wherein the exit comprises edges of each platform and one edge is displaced relative to the other edge.
12. An annular array of aerofoils as claimed in claim 11 wherein one edge is displaced above the other edge such that the coolant flow is presented adjacent to the junction gap downstream of the raised component edge.
13. A gas turbine engine including an annular array of aerofoils as claimed in claim 1.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An interconnect device comprising:
an interconnect die having no active components and configured to mount to an integrated circuit, the interconnect die including:
a plurality of substantially concentric electrically-conductive paths, each of the plurality of electrically-conductive paths being electrically isolated from each other and formed on a first surface of the interconnect die, at least one of the plurality of electrically-conductive paths arranged concentrically so as to substantially span a width of the first surface of the interconnect die; and
a first plurality of bonding pads electrically coupled to and distributed along each of the electrically-conductive paths, the first plurality of bonding pads coupled to one of the electrically-conductive paths being electrically isolated from bonding pads located on any other electrically-conductive path.
2. The interconnect device of claim 1, further comprising a second plurality of bonding pads, the second plurality of bonding pads being located on a periphery of the first surface of the interconnect die, the second plurality of bonding pads being electrically isolated from each other and from the first plurality of bonding pads.
3. The interconnect device of claim 2 wherein the first and second plurality of bonding pads are aluminum.
4. The interconnect device of claim 1 wherein the interconnect die is a die from a silicon wafer.
5. The interconnect device of claim 1 wherein the electrically-conductive paths are aluminum.
6. The interconnect device of claim 1 wherein the electrically-conductive paths are copper.
7. The interconnect device of claim 1 wherein the first and second plurality of bonding pads are copper.
8. The interconnect device of claim 1 wherein the interconnect die is configured to be mounted in proximity to a semiconductor device, the interconnect die being further configured to electrically couple to the semiconductor device.
9. The interconnect device of claim 1 wherein the interconnect device is configured to be mounted in proximity to a plurality of stacked semiconductor devices, the interconnect die being further configured to electrically couple to the semiconductor devices.
10. The interconnect device of claim 1 wherein the interconnect device is configured to electrically couple passive electrical components between at least two of the first plurality of bonding pads.
11. The interconnect device of claim 1 wherein the interconnect device is configured to electrically couple active electrical components between at least two of the first plurality of bonding pads.
12. The interconnect device of claim 1 wherein the interconnect device is configured to a particular package type by adding interconnects between at least two of the first plurality of bonding pads.
13. An integrated circuit package, comprising:
an interconnect die having no active components and configured to mount an integrated circuit, the interconnect die including
(i) a substrate;
(ii) a plurality of substantially concentric electrically-conductive paths, each of the plurality of electrically-conductive paths being electrically isolated from each other and formed on a first surface of the substrate, at least one of the plurality of the electrically-conductive paths arranged concentrically so as to substantially span a width of the first surface of the substrate;
(iii) a first plurality of bonding pads electrically coupled to and distributed along each of the electrically-conductive paths, the first plurality of bonding pads coupled to one of the electrically-conductive paths being electrically isolated from bonding pads located on any other electrically-conductive path; and
a leadframe package, the leadframe package having a plurality of metal leads, each of the plurality of metal leads having a first end and a second end, the second end being configured to be used as a package lead to electrically communicate external to the package, at least a portion of the first end electrically coupled to the interconnect die.
14. The integrated circuit package of claim 13, further comprising a second plurality of bonding pads on the interconnect die, the second plurality of bonding pads being located on a periphery of the first surface of the substrate, the second plurality of bonding pads being electrically isolated from each other and from the first plurality of bonding pads.
15. The integrated circuit package of claim 13 wherein the interconnect die is configured to be mounted on top of a semiconductor device, the interconnect die being further configured to electrically couple to the semiconductor device.
16. The integrated circuit package of claim 13 wherein the interconnect die is configured to be mounted on top of a plurality of stacked semiconductor devices, the interconnect die being further configured to electrically couple to the semiconductor devices.
17. The interconnect die of claim 13 wherein the interconnect die is configured to electrically couple passive electrical components between at least two of the first plurality of bonding pads.
18. The interconnect die of claim 13 wherein the interconnect die is configured to electrically couple active electrical components between at least two of the first plurality of bonding pads.
19. The interconnect die of claim 13 wherein the interconnect die is configured to a particular package type by adding interconnects between at least two of the first plurality of bonding pads.
20. An interconnect device comprising:
an interconnect die having no active components and configured to mount to a first integrated circuit, the interconnect die also configured to mount to either a second integrated circuit or a second interconnect die, the interconnect die including:
a plurality of substantially concentric electrically-conductive paths, each of the plurality of electrically-conductive paths being electrically isolated from each other and formed on a first surface of the interconnect die, at least one of the plurality of electrically-conductive paths arranged concentrically so as to substantially span a width of the first surface of the interconnect die; and
a first plurality of bonding pads electrically coupled to and distributed along each of the electrically-conductive paths, the first plurality of bonding pads coupled to one of the electrically-conductive paths being electrically isolated from bonding pads located on any other electrically-conductive path.
21. The interconnect die of claim 20, further comprising a second plurality of bonding pads, the second plurality of bonding pads being located on a periphery of the first surface of the interconnect die, the second plurality of bonding pads being electrically isolated from each other and from the first plurality of bonding pads.
22. The interconnect device of claim 21 wherein the first and second plurality of bonding pads are aluminum.
23. The interconnect device of claim 20 wherein the interconnect device is a die from a silicon wafer.
24. The interconnect device of claim 20 wherein the electrically-conductive paths are aluminum.
25. The interconnect device of claim 20 wherein the electrically-conductive paths are copper.
26. The interconnect device of claim 20 wherein the first and second plurality of bonding pads are copper.
27. The interconnect device of claim 20 wherein the interconnect device is configured to be electrically coupled to the first integrated circuit.
28. The interconnect device of claim 20 wherein the interconnect die is configured to electrically couple passive electrical components between at least two of the first plurality of bonding pads.
29. The interconnect device of claim 20 wherein the interconnect die is configured to electrically couple active electrical components between at least two of the first plurality of bonding pads.
30. An interconnect device comprising:
an interconnect die including:
a plurality of substantially concentric electrically-conductive paths, each of the plurality of electrically-conductive paths being electrically isolated from each other and formed on a first surface of the interconnect die, at least one of the plurality of electrically-conductive paths arranged concentrically so as to substantially span a width of the first surface of the interconnect die; and
a plurality of bonding pads electrically coupled to and distributed along each of the electrically conductive paths, a first plurality of bonding pads coupled to one of the electrically-conductive paths being electrically isolated from bonding pads located on any other electrically-conductive path, a second plurality of bonding pads being located on a periphery of the first surface of the interconnect die, at least one of the first plurality of bonding pads electrically coupled to at least one of the second plurality of bonding pads by an interconnect.
31. The interconnect device of claim 30 wherein the interconnect die is a die from a silicon wafer.
32. The interconnect device of claim 30 wherein the electrically-conductive paths are aluminum.
33. The interconnect device of claim 30 wherein the electrically-conductive paths are copper.
34. The interconnect device of claim 30 wherein the first and second plurality of bonding pads are aluminum.
35. The interconnect device of claim 30 wherein the interconnect die is configured to be mounted in proximity to a semiconductor device, the interconnect die being further configured to electrically couple to the semiconductor device.
36. The interconnect device of claim 30 wherein the interconnect device is configured to be mounted in proximity to a plurality of stacked semiconductor devices, the interconnect die being further configured to electrically couple to the semiconductor devices.
37. The interconnect device of claim 30 wherein the interconnect device is configured to electrically couple passive electrical components between at least two of the first plurality of bonding pads.
38. The interconnect device of claim 30 wherein the interconnect device is configured to electrically couple active components between at least two of the first plurality of the first plurality of bonding pads.
39. The interconnect device of claim 30 wherein the interconnect device is configured to electrically couple active electrical components between at least two of the first plurality of bonding pads.
40. The interconnect device of claim 30 further comprising the interconnect device incorporated into an integrated circuit package, the integrated circuit package including a leadframe package, the leadframe package having a plurality of metal leads, each of the plurality of metal leads having a first end and a second end, the second end being configured to be used as a package lead to electrically communicate external to the package, at least a portion of the first end electrically coupled to the interconnect die.