1. A switched capacitor amplifier circuit comprising:
an operational amplifier having a first input terminal and a second input terminal;
a first sampling capacitor being connected between an input signal and said first input terminal in a first phase; and
a first reference capacitor being coupled between said first input terminal and a reference voltage in said first phase, said first reference capacitor being connected between said first input terminal and a non-zero voltage in a second phase.
2. The switched capacitor amplifier circuit of claim 1, wherein said non-zero voltage represents said reference voltage but with opposite polarity.
3. The switched capacitor amplifier circuit of claim 2, further comprising:
a first feedback capacitor connected between said first input terminal and a first output terminal of said operational amplifier in said second phase,
wherein said first sampling capacitor is connected between a common mode reference voltage and said first input terminal in said second phase,
whereby the output (Vout) of said operational amplifier equals:
Vout
=
Cs
\u2062
\u2062
1
Cf
\xd7
(
Vinp
–
Vcm
)
–
Cs
\u2062
\u2062
2
Cf
\u2062
(
V
REF
–
V
1
)
wherein Cs1, Cs2 and Cf respectively represent the capacitance values of said first sampling capacitor, said first reference capacitor, and said first feedback capacitor, and Vinp, Vcm, Vref, and V1 respectively represent the voltage levels of said input signal, said common mode reference voltage, said reference voltage, and said non-zero voltage.
4. The switched capacitor amplifier circuit of claim 3, wherein Vcm is equal to 0 and V1 is equal to-Vref.
5. The switched capacitor amplifier circuit of claim 3, wherein said operational amplifier is operated in a differential mode, wherein Vref is equal to a difference between said reference voltage and said reference voltage with opposite polarity, V1 is equal to -Vref, and Vcm is equal to a common mode voltage of said input signal.
6. A device comprising:
a processor processing a plurality of digital values;
a switched capacitor amplifier circuit receiving an input signal and generating an amplified signal, each of said plurality of digital values being generated from said amplified signal, said switched capacitor amplifier circuit comprising:
an operational amplifier having a first input terminal and a second input terminal;
a first sampling capacitor being connected between an input signal and said first input terminal in a first phase; and
a first reference capacitor being coupled between said first input terminal and a reference voltage in said first phase, said first reference capacitor being connected between said first input terminal and a non-zero voltage in a second phase.
7. The device of claim 6, wherein said non-zero voltage represents said reference voltage but with opposite polarity.
8. The device of claim 7, further comprising:
a first feedback capacitor connected between said first input terminal and a first output terminal of said operational amplifier in said second phase,
wherein said first sampling capacitor is connected between a common mode reference voltage and said first input terminal in said second phase,
whereby the output (Vout) of said operational amplifier equals:
Vout
=
Cs
\u2062
\u2062
1
Cf
\xd7
(
Vinp
–
Vcm
)
–
Cs
\u2062
\u2062
2
Cf
\u2062
(
VREF
–
V
\u2062
\u2062
1
)
wherein Cs1, Cs2 and Cf respectively represent the capacitance values of said first sampling capacitor, said first reference capacitor, and said first feedback capacitor, and Vinp, Vcm, Vref, and V1 respectively represent the voltage levels of said input signal, said common mode reference voltage, said reference voltage, and said non-zero voltage.
9. The device of claim 8, wherein Vcm is equal to 0 and V1 is equal to -Vref.
10. The device of claim 8, wherein said operational amplifier is operated in a differential mode, wherein Vref is equal to a difference between said reference voltage and said reference voltage with opposite polarity, V1 is equal to -Vref, and Vcm is equal to a common mode voltage of said input signal.
11. The device of claim 6, wherein said switched capacitor amplifier circuit is comprised in a analog to digital converter (ADC).
12. The device of claim 11, further comprising:
a low noise amplifier receiving an external signal and generating an amplified signal;
a mixer down-converting said amplified signal using a carrier signal to generate a down-converted signal; and
a filter circuit filtering undesired components from said down-converted signal to generate said input signal;
wherein said ADC converts said input signal into said plurality of digital values.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An image reading apparatus comprising:
a scanner unit which optically scans an original;
a drive unit which moves said scanner unit;
a mode setting unit which sets between a normal processing mode and a high-speed processing mode; and
a controller,
wherein when an operation of reading an image of the original has been completed,
in said normal processing mode, said controller controls said drive unit to move said scanner unit to a home position, and thereafter sets an energized electric power of said drive unit at a minimum electric power, and keeps an energized state of said drive unit for a predetermined period of time, wherein when said controller is instructed to start a reading of an image of a succeeding original within the predetermined period of time, said controller performs a shading compensation for compensating an output of said scanner unit, and thereafter performs an operation of reading the image of the succeeding original, and
in said high speed processing mode, said controller sets the energized electric power of said drive unit at the minimum electric power without moving said scanner unit to the home position, and keeps the energized state of said drive unit for the predetermined period of time, wherein when said controller is instructed to start the reading of the image of the succeeding original within the predetermined period of time, said controller performs the operation of reading the image of the succeeding original without performing the shading compensation.
2. An image reading apparatus according to claim 1, wherein when the predetermined period of time has elapsed,
in said normal processing mode, said controller turns off an electric current to said drive unit, and
in said high-speed processing mode, said controller controls said drive unit to move said scanner unit to the home position, and thereafter turns off the electric current to said drive unit.
3. An image reading apparatus according to claim 1, wherein when said controller is instructed to start a reading of an image of the original after an electric power is applied to said image reading apparatus, said controller controls said drive unit to move said scanner unit to perform a home position search to initialize a position of said scanner unit for position setting, and thereafter performs an operation of reading the image of the original.
4. An image reading apparatus according to claim 1, further comprising a time setting unit which sets the predetermined period of time.
5. An image forming apparatus comprising:
an image reading apparatus as recited in claim 1; and
an image forming unit which records image information read by said image reading apparatus on a sheet.
6. A method of reading an image by using an image reading apparatus including a scanner unit which optically scans an original, a drive unit which moves said scanner unit, and a mode setting unit which sets between a normal processing mode and a high-speed processing mode, said method comprising:
when an operation of reading an image of the original has been completed in said normal processing mode, controlling said drive unit to move said scanner unit to a home position, and thereafter setting an energized electric power of said drive unit at a minimum electric power, and keeping an energized state of said drive unit for a predetermined period of time, wherein when instructed to start a reading of an image of a succeeding original within the predetermined period of time, performing a shading compensation for compensating an output of said scanner unit, and thereafter performing an operation of reading the image of the succeeding original, and
when the operation of reading the image of the original has been completed in said high-speed processing mode, setting the energized electric power of said drive unit at the minimum electric power without moving said scanner unit to the home position, and keeping the energized state of said drive unit for the predetermined period of time, wherein when instructed to start the reading of the image of the succeeding original within the predetermined period of time, performing the operation of reading the image of the succeeding original without performing the shading compensation.