1. A power management method for use in an electronic device, comprising the steps of:
a) providing a first section which stores volatile data and is capable of entering a low power consumption state;
b) providing a second section which can automatically and regularly power itself up and down;
c) providing a power source powering both the first and the second sections;
d) powering the first section up from the low power consumption state to a powered up state, automatically; and
e) assessing, using a power management algorithm operating on the first section in the powered up state to assess whether both the first and the second sections should be taken to a low power consumption state.
2. The method of claim 1 in which the power management algorithm causes both the first and the second section to be taken to a low power consumption state on the basis of an inference of likely future power consumption based on pre-defined figures.
3. The method of claim 1 in which the power management algorithm causes both the first and the second section to be taken to a low power consumption state on the basis of a calculation of actual power usage.
4. The method of claim 1 in which the power management algorithm is operable to cause the elapsed time before the first section is automatically revived from sleep to be varied.
5. The method of claim 1 in which the first section can vary at least one parameter relating to the power consumption of the second section in dependence on an output from the power management algorithm.
6. The method of claim 1 in which the first section comprises a computing device and the second section comprises a communications device.
7. The method of claim 1 in which the second section automatically and regularly powers itself up and down as part of a camping process.
8. An electronic device programmed to perform a power management method, in which the device comprises a first section which stores volatile data and is capable of entering a low power consumption state and a second section which can automatically and regularly power itself up and down, and a power source powering both the first and the second sections;
wherein the first section powers itself up from a low power consumption state automatically and a power management algorithm then operates to assess whether both the first and the second sections should be taken to a low power consumption state.
9. The device of claim 8 in which the power management algorithm causes both the first and the second section to be taken to a low power consumption state on the basis of an inference of likely future power consumption based on pre-defined figures.
10. The device of claim 8 in which the power management algorithm causes both the first and the second section to be taken to a low power consumption state on the basis of a calculation of actual power usage.
11. The device of claim 8 in which the power management algorithm is operable to cause the elapsed time before the first section is automatically revived from sleep to be varied.
12. The device of claim 8 in which the first section can vary one or more parameters relating to the power consumption of the second section in dependence on an output from the power management algorithm.
13. The device of claim 8 in which the first section comprises a computing device and the second section comprises a communications device.
14. The device of claim 8 in which the second section automatically and regularly powers itself up and down as part of a camping process.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A calibrator comprising:
a first Digital-to-Analog converter;
a second Digital-to-Analog converter;
a first resistor coupled between a power supply voltage and a calibrator output having an adjustable value controlled by the first Digital-to-Analog converter;
a second resistor coupled between the calibrator output and ground having an adjustable value controlled by the first Digital-to-Analog converter; and
a set resistor coupled between an output of the second Digital-to-Analog converter and ground, wherein the current flowing through the set resistor is sourced from the calibrator output.
2. The calibrator of claim 1 wherein the first Digital-to-Analog converter receives an input word having a first number of bits.
3. The calibrator of claim 2 wherein the input word comprises three bits.
4. The calibrator of claim 2 wherein the second Digital-to-Analog converter receives an input word having a second number of bits.
5. The calibrator of claim 4 wherein the input word comprises seven bits.
6. The calibrator of claim 1 wherein the first resistor comprises a programmable integrated circuit resistor.
7. The calibrator of claim 1 wherein the second resistor comprises a programmable integrated circuit resistor.
8. The calibrator of claim 1 wherein the set resistor comprises a programmable integrated circuit resistor.
9. The calibrator of claim 1 further comprising an interface and control logic block for receiving a clock signal and a data input signal, for providing a first digital input signal for the first Digital-to-Analog converter, and for providing a second digital input signal for the second Digital-to-Analog converter.
10. The calibrator of claim 9 further comprising a non-volatile memory coupled to the interface and control logic block.
11. The calibrator of claim 1 further comprising a buffer having a first input coupled to the second Digital-to-Analog converter, a second input coupled to the set resistor, and a current output coupled to the calibrator output.
12. The calibrator of claim 1 further comprising a buffer coupled to the calibrator output.
13. The calibrator of claim 1 further comprising changing an output value of the first Digital-to-Analog converter to select a sub-range that contains a desired calibrator output value.
14. The calibrator of claim 1 wherein the desired calibrator output value is between one-third and two-thirds of the power supply voltage.
15. The calibrator of claim 13 further comprising changing an output value of the second Digital-to-Analog converter to achieve the desired calibrator output value.
16. A calibration method comprising:
providing a first Digital-to-Analog converter;
providing a second Digital-to-Analog converter;
coupling a first resistor between a power supply voltage and a calibrator output having an adjustable value controlled by the first Digital-to-Analog converter;
coupling a second resistor coupled between the calibrator output and ground having an adjustable value controlled by the first Digital-to-Analog converter;
coupling a set resistor between an output of the second Digital-to-Analog converter and ground; and
sourcing the current flowing through the set resistor is from the calibrator output.
17. The method of claim 16 further comprising changing an output value of the first Digital-to-Analog converter to select a sub-range that contains a desired calibrator output value.
18. The method of claim 17 wherein the desired calibrator output value is between one-third and two-thirds of the power supply voltage.
19. The method of claim 17 further comprising changing an output value of the second Digital-to-Analog converter to achieve the desired calibrator output value.
20. A calibrator comprising:
a first resistor, a second resistor, and set resistor in an integrated circuit having an adjustable value controlled by a first Digital-to-Analog converter;
a resistor divider formed by the first and second resistors having a calibrator output; and
a second Digital-to-Analog converter for controlling the voltage across the set resistor, wherein the current through the set resistor is sourced from the calibrator output.