1. A method for forming a metal line, comprising the steps of:
forming a metal structure on a substrate;
forming a dual hard mask on the metal structure;
forming a photoresist pattern on the dual hard mask;
patterning the dual hard mask by using the photoresist pattern as an etch mask; and
patterning the metal structure by using the dual hard mask, thereby obtaining the metal line.
2. The method of claim 1, wherein the dual hard mask includes a tungsten layer and a nitride layer.
3. The method of claim 1, wherein the metal structure includes a single layer based on a material selected one of titanium nitride (TiN) and aluminum (Al).
4. The method of claim 1, wherein the metal structure includes stack layers of TiN and Al.
5. The method of claim 1, wherein the photoresist pattern is formed by employing an ArF photolithography process.
6. The method of claim 1, wherein the photoresist pattern is formed by employing a KrF photolithography process.
7. The method of claim 1, further including the step of forming an anti-reflective coating layer on the dual hard mask.
8. A method for forming a metal line in a semiconductor memory device having a word line strapping structure, the method comprising the steps of:
sequentially forming at least more than one metal layer, an insulation layer for forming a first sacrificial hard mask, a tungsten layer for forming a second sacrificial hard mask, and an anti-reflective coating layer on a substrate;
forming a photoresist pattern on the anti-reflective coating layer;
etching the anti-reflective coating layer by using the photoresist pattern as an etch mask;
etching the tungsten layer with use of the photoresist pattern as an etch mask, thereby forming the second sacrificial hard mask;
etching the insulation layer with use of the second sacrificial hard mask as an etch mask, thereby forming the first sacrificial hard mask;
etching said at least more than one metal layer with use of the first and the second sacrificial hard masks, thereby forming a metal line; and
removing the first and the second sacrificial hard masks.
9. The method of claim 8, wherein the insulation layer for forming the first sacrificial hard mask is made of a material selected from oxide and nitride.
10. The method of claim 8, further including the step of removing the photoresist pattern and the anti-reflective coating layer after the step of forming the first sacrificial hard mask.
11. The method of claim 8, wherein the anti-reflective coating layer is made of an organic material.
12. The method of claim 8, wherein said at least more than one metal layer is a single layer based on a material selected from titanium nitride (TiN) and aluminum (Al).
13. The method of claim 8, wherein said at least more than one metal layer includes stack layers of TiN and Al.
14. The method of claim 8, wherein the step of forming the photoresist pattern proceeds by employing an ArF photolithography process.
15. The method of claim 8, wherein the step of forming the photoresist pattern proceeds by employing a KrF photolithography process.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device package comprising:
a substrate;
a first dielectric layer disposed over a surface of the substrate;
a conductive trace layer disposed over the first dielectric layer;
an upper dielectric layer disposed over the conductive trace layer, the upper dielectric layer defining a plurality of openings therethrough exposing a plurality of connection areas on the conductive trace layer;
a plurality of semiconductor dice, each semiconductor die of the plurality of semiconductor dice having a plurality of signal connection devices, wherein the plurality of signal connection devices is electrically coupled with the conductive trace layer through the plurality of openings; and
a plurality of circuit connection elements electrically coupled to the conductive trace layer, wherein each of the plurality of circuit connection elements extends through the upper dielectric layer.
2. The semiconductor device package of claim 1, wherein the plurality of semiconductor dice include at least two semiconductor dice having different functions.
3. The semiconductor device package of claim 1, further comprising an attachment layer overlaying at least a portion of the upper dielectric layer and the conductive trace layer and disposed between the upper dielectric layer and at least one of the plurality of semiconductor dice.
4. The semiconductor device package of claim 3, wherein the attachment layer is selected from the group consisting of anisotropic conducting film, anisotropic conducting paste, nonconductive film, and nonconductive paste.
5. The semiconductor device package of claim 1, further comprising an encapsulation layer disposed over the plurality of semiconductor dice wherein at least an exposed portion of the plurality of circuit connection elements is exposed through the encapsulation layer.
6. The semiconductor device package of claim 5, further comprising a plurality of conductive bumps wherein each conductive bump of the plurality of conductive bumps is electrically coupled with the exposed portion of one of the plurality of circuit connection elements.
7. The semiconductor device package of claim 6, wherein the plurality of conductive bumps is selected from the group consisting of solder bumps, gold stud bumps, copper stud bumps, and plated alloy stud bumps.
8. A semiconductor device package comprising:
a substrate;
a plurality of redistribution layers disposed over a surface of the substrate and configured for operably coupling to a lower redistribution layer of the plurality of redistribution layers, each routing layer of the plurality of redistribution layers comprising:
a dielectric layer comprising a plurality of vias formed therethrough; and
a conductive trace layer disposed over the dielectric layer and in the plurality of vias;
an upper dielectric layer disposed over a top redistribution layer of the plurality of redistribution layers, the upper dielectric layer defining a plurality of openings therethrough exposing a plurality of connection areas on the top redistribution layer;
a plurality of semiconductor dice, each semiconductor die of the plurality of semiconductor dice having a plurality of signal connection devices, wherein the plurality of signal connection devices is electrically coupled with the top redistribution layer through the plurality of openings; and
a plurality of circuit connection elements electrically coupled to the conductive trace layer, wherein each of the plurality of circuit connection elements extends through the plurality of redistribution layers and the upper dielectric layer.
9. The semiconductor device package of claim 8, wherein the plurality of semiconductor dice include at least two semiconductor dice having different functions.
10. The semiconductor device package of claim 8, further comprising an attachment layer overlaying at least a portion of the upper dielectric layer and the top redistribution layer and disposed between the upper dielectric layer and at least one of the plurality of semiconductor dice.
11. The semiconductor device package of claim 10, wherein the attachment layer is selected from the group consisting of anisotropic conducting film, anisotropic conducting paste, nonconductive film, and nonconductive paste.
12. The semiconductor device package of claim 8, further comprising an encapsulation layer disposed over the plurality of semiconductor dice wherein at least an exposed portion of the plurality of circuit connection elements is exposed through the encapsulation layer.
13. The semiconductor device package of claim 12, further comprising a plurality of conductive bumps wherein each conductive bump of the plurality of conductive bumps is electrically coupled with the exposed portion of one of the plurality of circuit connection elements.
14. The semiconductor device package of claim 13, wherein the plurality of conductive bumps is selected from the group consisting of solder bumps, gold stud bumps, copper stud bumps, and plated alloy stud bumps.
15. A computing system comprising:
a carrier substrate;
a processor operably coupled to the carrier substrate;
at least one input device operably coupled with the processor;
at least one output device operably coupled with the processor; and
a memory device operably coupled to circuitry formed in the carrier substrate, the memory device including at least one semiconductor device package, the at least one semiconductor device package comprising:
a substrate;
a first dielectric layer disposed over a surface of the substrate;
a conductive trace layer disposed over the first dielectric layer;
an upper dielectric layer disposed over the conductive trace layer, the upper dielectric layer defining a plurality of openings therethrough exposing a plurality of connection areas on the conductive trace layer;
a plurality of semiconductor dice, each semiconductor die of the plurality of semiconductor dice having a plurality of signal connection devices, wherein the plurality of signal connection devices is electrically coupled with the conductive trace layer through the plurality of openings; and
a plurality of circuit connection elements electrically coupled to the conductive trace layer, wherein each of the plurality of circuit connection elements extends through the upper dielectric layer.
16. The computing system package of claim 15, wherein the plurality of semiconductor dice include at least two semiconductor dice having different functions.
17. The computing system of claim 15, further comprising an attachment layer overlaying at least a portion of the upper dielectric layer and the conductive trace layer and disposed between the upper dielectric layer and at least one of the plurality of semiconductor dice.
18. The computing system of claim 17, wherein the attachment layer is selected from the group consisting of anisotropic conducting film, anisotropic conducting paste, nonconductive film, and nonconductive paste.
19. The computing system of claim 15, further comprising an encapsulation layer disposed over the plurality of semiconductor dice wherein at least an exposed portion of the plurality of circuit connection elements is exposed through the encapsulation layer.
20. The computing system of claim 19, further comprising a plurality of conductive bumps wherein each conductive bump of the plurality of conductive bumps is electrically coupled with the exposed portion of one of the plurality of circuit connection elements.
21. The computing system of claim 20, wherein the plurality of conductive bumps is selected from the group consisting of solder bumps, gold stud bumps, copper stud bumps, and plated alloy stud bumps.