1. A memory device, comprising:
an array of memory cells, each memory cell comprising a memory element programmable between a first memory state and a second memory state;
a decoder electrically coupled to one or more word lines comprised in the array of memory cells, the decoder configured to decode an address input to select a word line of the one or more word lines comprised in the array of memory cells;
a binarizer electrically coupled to the array of memory cells and configured to receive a plurality of memory cell outputs from the array of memory cells and generate a plurality of binary weighted memory cell outputs in response to the decoder selecting a word line of the one or more word lines of the array of memory cells, wherein each binary weighted memory cell output corresponds with one memory cell;
a summer electrically coupled to the binarizer and configured to sum the binary weighted memory cell outputs into an analog signal; and
a quantizer electrically coupled to the summer and configured to convert the analog signal into a digital output.
2. The device of claim 1, wherein the binarizer comprises a voltage clamping transistor and at least one pair of load transistors and the pair of load transistors is configured to binarily weight and amplify, through a current mirror, a current corresponding with a memory cell.
3. The device of claim 1, wherein the digital output is a plurality of data bits corresponding with data stored on memory cells of a word line of the one or more word lines of the array of memory cells.
4. The device of claim 1, wherein a read data path of the memory device comprises a (4+m)n bit data path which comprises (4+m)n memory cells, (4+m)n clamp transistors, (4+m)n weighted current mirrors, a (4+m)n input summer and a (4+m)n bit quantizer, and wherein the memory device is configured to resolve (4+m)n bits of stored data simultaneously, wherein m is an integer and n is a positive integer.
5. The device of claim 1, further comprising a plurality of arrays of memory cells and a plurality of bit line select blocks, each array of memory cells forming a macro portion, each macro portion electrically coupled to one of the bit line select blocks and further coupled to a first decoder through word lines, where the first decoder is configured to decode one of a first and second address input to select a word line, and wherein each bit line select block is coupled to a second decoder configured to decode a third address input to select one of the bit line select blocks.
6. The device of claim 1, wherein a plurality of arrays of memory cells form a plurality of identical parallel (4+m) bit read data paths to generate (4+m)n output data bits, where m is an integer and n is a positive integer corresponding with the number of identical parallel (4+m) bit read data paths.
7. The device of claim 1, wherein the memory device comprises: four 4\xd74 arrays of memory cells; four bit line select blocks, each bit line select block electrically coupled to one 4\xd74 array of memory cells; two binarizers, each binarizer electrically coupled to two bit line select blocks; two summers, each summer electrically coupled to one binarizer; and two 4-bit current quantizers, each 4-bit current quantizer coupled to one summer.
8. The device of claim 1, wherein the memory elements each comprise an isolation transistor.
9. The device of claim 1, wherein the memory elements each include a magnetic tunnel junction.
10. A method of using a memory device, comprising:
decoding a word line address of an array of memory cells through a decoder and selecting the decoded word line, each memory cell comprising memory element programmable between a first memory state and a second memory state;
applying a control voltage to clamp transistors coupled to memory cells of the selected word line;
assigning binary weights to bit line currents to form binary weighted bit line currents;
summing the binary weighted bit line currents to generate an analog output current; and
quantizing the analog output current into a 4n bit digital code through a current quantizer, where n is a positive integer.
11. The method of claim 10, further comprising decoding at least one group of (4+m)n bit line addresses of the array of memory cells and selecting the decoded bit lines, and applying the control voltage to clamp transistors coupled to memory cells of the selected bit lines, wherein m is an integer and n is a positive integer.
12. The method of claim 10, wherein assigning weights to bit line currents comprises passing each bit line current through a pair of load transistors configured to binarily weight the bit line current through a current mirror.
13. The method of claim 10, further comprising amplifying the bit line currents.
14. The method of claim 10, further comprising providing a plurality of arrays of memory cells, each array of memory cells forming a macro portion, and providing a plurality of bit line select blocks and electrically coupling each macro portion to one of the bit line select blocks and further coupling each macro portion to a first decoder through word lines where the first decoder is configured to decode one of a first and second address input to select a word line, and further coupling each bit line select block to a second decoder configured to decode a third address input to enable selection of one of the bit line select blocks.
15. The method of claim 10, further comprising decoding an address associated with a bit line select block through a second decoder and selecting a bit line select block associated with that address.
16. A method of using a memory device, comprising:
decoding a word line address of an array of memory cells through a decoder and selecting the decoded word line, each memory cell comprising a memory element programmable between a first memory state and a second memory state;
applying a current to memory cells of the selected word line;
assigning binary weights to bit line voltages to form binary weighted bit line voltages;
summing the binary weighted bit line voltages to generate an analog output voltage; and
quantizing the analog output voltage into a (4+m)n bit digital code through a quantizer, wherein m is an integer and n is a positive integer.
17. The method of claim 16, further comprising decoding at least one group of (4+m)n bit line addresses of the array of memory cells, selecting the decoded bit lines, and applying the current to clamp transistors coupled to memory cells of the selected bit lines, wherein in is an integer and n is a positive integer.
18. The method of claim 16, wherein assigning binary weights to bit line voltages comprises assigning binary weights to bit line voltages with voltage multipliers.
19. The method of claim 16, further comprising:
providing a plurality of arrays of memory cells, each array of memory cells forming a macro portion;
providing a plurality of bit line select blocks;
electrically coupling each macro portion to one of the bit line select blocks and further coupling each macro portion to a first decoder through word lines, where the first decoder is configured to decode one of a first and a second address input to select a word line; and
coupling each bit line select block to a second decoder configured to decode a third address input to enable selection one of the bit line select blocks.
20. The method of claim 16, further comprising decoding an address associated with a bit line select block through a second decoder and selecting a bit line select block associated with that address.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A storage device comprising:
a nonvolatile semiconductor memory configured to store a plurality of first correcting codes to respectively correct errors in a plurality of first data blocks, a second correcting code to correct errors in a second data block which comprises the first data blocks, and the second data block, wherein
when data is read out from the nonvolatile semiconductor memory, a first error correction processing is performed first by using the first correcting code,
if the first error correction processing is unsuccessful, a second error correction processing is performed by using the second correcting code, and
if the first error correction processing is successful, the second error correction processing is not performed.
2. The device according to claim 1, further comprising:
a first corrector configured to correct errors in the first data blocks using the first correcting codes; and
a second corrector configured to correct errors in the second data block using the second correcting code.
3. The device according to claim 1, wherein the nonvolatile semiconductor memory is a NAND flash memory.
4. A storage device comprising:
a nonvolatile semiconductor memory configured to store data; and
an error correction circuit configured to correct an error when reading the data stored in the nonvolatile semiconductor memory,
wherein a correction capability of data is increased due to the increase in the number of errors of the data stored in the nonvolatile semiconductor memory.
5. The device according to claim 4, further comprising:
a first correcting code generator configured to generate a first correcting code to correct error in a first data block; and
a second correcting code generator configured to generate a second correcting code to correct error in a second data block, the second data block comprising first data blocks,
wherein the nonvolatile semiconductor memory is configured to store the second data block, first correcting codes, and the second correcting code.
6. The device according to claim 5, wherein
the error correction circuit includes:
a first corrector configured to correct errors in the first data blocks using the first correcting codes; and
a second corrector configured to correct errors in the second data block using the second correcting code.
7. The device according to claim 4, wherein the nonvolatile semiconductor memory is a NAND flash memory.