1. A linear motion device comprising:
a rod extending along a longitudinal axis; and
a plurality of actuator units, with each of the plurality of actuator units including at least one Shape Memory Alloy (SMA) element attached to a coupler, wherein the at least one SMA element of each of the plurality of actuator units moves the coupler along the longitudinal axis and into grasping engagement with the rod to move the rod a unit movement distance along the longitudinal axis in response to a control signal;
wherein the plurality of actuator units are actuated repeatedly in a synchronous order to move the rod in a continuous linear motion a distance greater than the unit movement distance of each of the plurality of actuator units;
wherein each of the plurality of actuator units includes a first coupler and a second coupler disposed on opposite sides of the rod; and
wherein the at least one SMA element includes a connecting SMA element extending between and attached to both the first coupler and the second coupler and configured to contract to draw the first coupler and the second coupler together into grasping engagement with the rod in response to the signal.
2. A linear motion device as set forth in claim 1 wherein the at least one SMA element of each of the plurality of actuator units contracts in response to the control signal to move the coupler.
3. A linear motion device as set forth in claim 1 wherein the at least one SMA element of each of the plurality of actuator units elongates in response to the cessation of the control signal to release the coupler from the grasping engagement with the rod and allow the coupler to return to a neutral position.
4. A linear motion device as set forth in claim 1 wherein the at least one SMA element of each of the plurality of actuator units is operable to move the coupler and the rod in both a first direction parallel to the longitudinal axis, and a second direction parallel to the longitudinal axis, wherein the first direction is opposite the second direction.
5. A linear motion device as set forth in claim 4 wherein the at least one SMA element includes a first SMA element attached to the coupler for moving the coupler in the first direction, and a second SMA element attached to the coupler for moving the coupler in the second direction.
6. A linear motion device as set forth in claim 1 wherein each of the plurality of actuator units includes at least one spring.
7. A linear motion device as set forth in claim 1 wherein at least one of the rod and the coupler include a friction feature.
8. A linear motion device as set forth in claim 1 wherein each of the plurality of actuator units includes a housing, with the rod and the coupler moveable relative to the housing.
9. A linear motion device as set forth in claim 8 wherein the coupler is coupled to the housing.
10. A linear motion device as set forth in claim 1 wherein a first group of the plurality of actuator units may be actuated simultaneously to increase a moving force applied to the rod.
11. A linear motion device as set forth in claim 1 wherein the coupler includes a spring member.
12. A linear motion device as set forth in claim 1 wherein the coupler includes a lever arm.
13. A linear motion device as set forth in claim 1 wherein each of the plurality of actuator units may default to a normally engaged position disposed in grasping engagement with the rod, or a normally disengaged position not disposed in grasping engagement with the rod.
14. A linear actuator assembly for a linear motion device, the linear actuator assembly comprising:
a plurality of actuator units, with each of the actuator units including:
a housing;
a coupler; and
at least one Shape Memory Alloy (SMA) element attached to the coupler;
wherein the at least one SMA element moves the coupler from a neutral position along a longitudinal axis and into grasping engagement with a rod to move the rod a unit movement distance along the longitudinal axis in response to a control signal;
wherein the at least one SMA element of each of the plurality of actuator units contracts in response to the control signal to move the coupler; and
wherein the at least one SMA element of each of the plurality of actuator units elongates in response to the cessation of the control signal to release the coupler from the grasping engagement with the rod and allow the coupler to return to the neutral position;
wherein the plurality of actuator units are actuated repeatedly in a synchronous order to move the rod in a continuous linear motion a distance greater than the unit movement distance of each of the plurality of actuator units; and
wherein each of the plurality of actuator units includes a first coupler and a second coupler disposed on opposite sides of the rod, and wherein the at least one SMA element includes a connecting SMA element extending between and attached to both the first coupler and the second coupler and configured to contract to draw the first coupler and the second coupler together into grasping engagement with the rod in response to the signal.
15. A linear actuator assembly as set forth in claim 14 wherein each of the plurality of actuator units includes at least one spring.
16. A linear actuator assembly as set forth in claim 14 wherein each of the plurality of actuator units includes a housing, with the rod and the coupler moveable relative to the housing, and with the coupler coupled to the housing.
17. A linear actuator assembly as set forth in claim 14 wherein the at least one SMA element includes a first SMA element attached to the coupler for moving the coupler in a first direction parallel to the longitudinal axis, and a second SMA element attached to the coupler for moving the coupler in a second direction parallel to the longitudinal axis, wherein the first direction is opposite the second direction.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A compound junctionless field effect transistor comprising:
a bulk silicon substrate not having a buried oxide layer;
a blocking semiconductor layer formed of a first semiconductor material having a lattice constant difference with silicon 5% or less and doped to have a first conductive type on the silicon substrate;
an active layer formed of a second semiconductor material having a lattice constant difference with the first semiconductor material 2% or less, an electron affinity difference with the first semiconductor material 0.1 eV or less, and an energy bandgap 0.5 eV greater than that of the first semiconductor material and doped to have a second conductive type opposite to the first conductive type on the blocking semiconductor layer;
a gate electrode formed to be separated by a gate dielectric layer on the active layer; and
source and drain electrodes formed to contact electrically to the active layer with having a specific interval from each other and being separated by the gate electrode,
wherein a first heterojunction is formed between the bulk silicon substrate and the blocking semiconductor layer and a second heterojunction is formed between the blocking semiconductor layer and the active layer.
2. The compound junctionless field effect transistor of claim 1, wherein the second semiconductor material has electron or hole mobility higher than that of the silicon.
3. The compound junctionless field effect transistor of claim 2, wherein:
the active layer is projected to have one sidewall at least on the blocking semiconductor layer, and
the gate dielectric layer and the gate electrode are formed on the sidewall to have a vertical channel structure.
4. The compound junctionless field effect transistor of claim 3, wherein:
the active layer is projected to have a cylindrical column shaped sidewall on the blocking semiconductor layer, and
the gate dielectric layer and the gate electrode are formed to wrap the cylindrical column shaped sidewall.
5. The compound junctionless field effect transistor of claim 1, wherein:
the active layer is doped with doping concentration to have majority carriers of the second semiconductor material be in degenerate states but to make an energy band be sloped at an operation time, and
the blocking semiconductor layer is doped with doping concentration to have majority carriers of the first semiconductor material be in non-degenerate states.
6. The compound junctionless field effect transistor of claim 5, wherein:
the active layer is doped with an n-type dopant to have Fermi level be formed within 3 kT over the minimum value of conduction band of the second semiconductor material at an absolute temperature T, and
the blocking semiconductor layer is doped with a p-type dopant to have Fermi level be formed at 3 kT or higher energies over the maximum value of valance band of the first semiconductor material at an absolute temperature T.
7. The compound junctionless field effect transistor of claim 5, wherein:
the active layer is doped to have the second conductive type be an n-type and to have the doping concentration of the n-type dopant be 9\xd71016\u02dc1\xd71018cm3, and
the blocking semiconductor layer is doped to have the first conductive type be a p-type and to have the doping concentration of the p-type dopant be 3.4\xd71017cm3 or lower.
8. The compound junctionless field effect transistor of claim 5, wherein:
the first semiconductor material is germanium (Ge) or silicon germanium (Si1-xGex), and
the second semiconductor material is gallium arsenide (GaAs).
9. The compound junctionless field effect transistor of claim 2, wherein:
the active layer is doped with doping concentration to have majority carriers of the second semiconductor material be in degenerate states but to make an energy band be sloped at an operation time, and
the blocking semiconductor layer is doped with doping concentration to have majority carriers of the first semiconductor material be in non-degenerate states.
10. The compound junctionless field effect transistor of claim 9, wherein:
the active layer is doped with an n-type dopant to have Fermi level be formed within 3 kT over the minimum value of conduction band of the second semiconductor material at an absolute temperature T, and
the blocking semiconductor layer is doped with a p-type dopant to have Fermi level be formed at 3 kT or higher energies over the maximum value of valance band of the first semiconductor material at an absolute temperature T.
11. The compound junctionless field effect transistor of claim 9, wherein:
the active layer is doped to have the second conductive type be an n-type and to have the doping concentration of the n-type dopant be 9\xd71016\u02dc1\xd71018cm3, and
the blocking semiconductor layer is doped to have the first conductive type be a p-type and to have the doping concentration of the p-type dopant be 3.4\xd71017cm3 or lower.
12. The compound junctionless field effect transistor of claim 9, wherein:
the first semiconductor material is germanium (Ge) or silicon germanium (Si1-xGex), and
the second semiconductor material is gallium arsenide (GaAs).
13. The compound junctionless field effect transistor of claim 3, wherein:
the active layer is doped with doping concentration to have majority carriers of the second semiconductor material be in degenerate states but to make an energy band be sloped at an operation time, and
the blocking semiconductor layer is doped with doping concentration to have majority carriers of the first semiconductor material be in non-degenerate states.
14. The compound junctionless field effect transistor of claim 13, wherein:
the active layer is doped with an n-type dopant to have Fermi level be formed within 3 kT over the minimum value of conduction band of the second semiconductor material at an absolute temperature T, and
the blocking semiconductor layer is doped with a p-type dopant to have Fermi level be formed at 3 kT or higher energies over the maximum value of valance band of the first semiconductor material at an absolute temperature T.
15. The compound junctionless field effect transistor of claim 13, wherein:
the active layer is doped to have the second conductive type be an n-type and to have the doping concentration of the n-type dopant be 9\xd71016\u02dc1\xd71018cm3, and
the blocking semiconductor layer is doped to have the first conductive type be a p-type and to have the doping concentration of the p-type dopant be 3.4\xd71017cm3 or lower.
16. The compound junctionless field effect transistor of claim 13, wherein:
the first semiconductor material is germanium (Ge) or silicon germanium (Si1-xGex), and
the second semiconductor material is gallium arsenide (GaAs).
17. The compound junctionless field effect transistor of claim 4, wherein:
the active layer is doped with doping concentration to have majority carriers of the second semiconductor material be in degenerate states but to make an energy band be sloped at an operation time, and
the blocking semiconductor layer is doped with doping concentration to have majority carriers of the first semiconductor material be in non-degenerate states.
18. The compound junctionless field effect transistor of claim 17, wherein:
the active layer is doped with an n-type dopant to have Fermi level be formed within 3 kT over the minimum value of conduction band of the second semiconductor material at an absolute temperature T, and
the blocking semiconductor layer is doped with a p-type dopant to have Fermi level be formed at 3 kT or higher energies over the maximum value of valance band of the first semiconductor material at an absolute temperature T.
19. The compound junctionless field effect transistor of claim 17, wherein:
the active layer is doped to have the second conductive type be an n-type and to have the doping concentration of the n-type dopant be 9\xd71016\u02dc1\xd71018cm3, and
the blocking semiconductor layer is doped to have the first conductive type be a p-type and to have the doping concentration of the p-type dopant be 3.4\xd71017cm3 or lower.
20. The compound junctionless field effect transistor of claim 17, wherein:
the first semiconductor material is germanium (Ge) or silicon germanium (Si1-xGex), and
the second semiconductor material is gallium arsenide (GaAs).