1. A storage system comprising:
a first storage apparatus located at a first site;
a second storage apparatus located at a second site;
a third storage apparatus located at a third site; and
a network connecting the first, second, and third storage apparatuses to one another in a communication-enabling manner,
wherein, the first storage apparatus stores data transmitted from a host system and transmits the data to the second and the third storage apparatuses, and the first storage apparatus transmits a verification request command upon the first storage apparatus’ determination that a predetermined number of storage system access requests has occurred or a predetermined time has been exceeded, the first storage apparatus transmitting the verification request command to at least one of the second and the third storage apparatuses to instruct that a data consistency verification be conducted between the second and the third storage apparatuses; and
wherein the second and the third storage apparatuses individually store the data transmitted from the first storage apparatus, and
wherein at least one of the second and the third storage apparatuses are adapted to perform consistency verification operations responsive to the verification request command issued from the first storage apparatus, to verify the consistency in the data between the second and third storage apparatuses, wherein the first storage apparatus does not perform any of the consistency verification operations to verify the consistency in the data between the second and third storage apparatuses.
2. The storage system according to claim 1, wherein:
the first storage apparatus transmits the verification request command to at least one of the second and the third storage apparatuses at a predetermined timing; and
in response to this verification request command, the second and the third storage apparatuses verify the consistency in the data between the second and third storage apparatuses at a timing related to the predetermined timing.
3. The storage system according to claim 2, wherein the predetermined time concerns an elapsed time from the last transmission of the verification request command.
4. The storage system according to claim 1, wherein:
transmission of the data from the first storage apparatus to the second storage apparatus is conducted using a synchronous method;
transmission of the data from the first storage apparatus to the third storage apparatus is conducted using a synchronous method; and
upon the data consistency verification instructed by the verification request command, if the data stored in the second storage apparatus and the data stored in the third storage apparatus do not match, the data stored in the third storage apparatus is overwritten with the corresponding data stored in the second storage apparatus.
5. The storage system according to claim 1, wherein the first storage apparatus judges whether or not a failure has occurred in the second storage apparatus or the third storage apparatus, or whether or not a communication link between the second and the third storage apparatuses has been cut, on a basis of an existence or non-existence of an error in communication between the second storage apparatus and the third storage apparatus.
6. The storage system according to claim 1, wherein:
when a failure occurs in a faulty one of the second storage apparatus and the third storage apparatus, data in a non-faulty one of the second storage apparatus and third storage apparatus is transmitted to the faulty storage apparatus after recovery of the faulty storage apparatus; and
the faulty storage apparatus is recovered by storing the data transmitted from the other storage apparatus.
7. A backup method for a storage system including: a first storage apparatus located at a first site; a second storage apparatus located at a second site; a third storage apparatus located at a third site, and a network connecting the first, second, and third storage apparatuses to one another in a communication-enabling manner, the method comprising:
the first storage apparatus storing data transmitted from a host system and also transmitting the data to the second storage apparatus and the third storage apparatus, and the first storage apparatus transmitting a verification request command issued by the first storage apparatus upon the first storage apparatus’ determination that a predetermined number of storage system access requests has occurred or a predetermined time has been exceeded, the first storage apparatus transmitting the verification request command to at least one of the second and the third storage apparatuses to instruct that a data consistency verification be conducted between the second and the third storage apparatuses;
the second storage apparatus and the third storage apparatus storing, individually, the data transmitted from the first storage apparatus, and
at least one of the second and the third storage apparatuses performing consistency verification operations for verifying a consistency in the data between the second and third storage apparatuses responsive to the verification request command issued from the first storage apparatus, wherein the first storage apparatus does not perform any of the consistency verification operations to verify the consistency in the data between the second and third storage apparatuses.
8. The backup method according to claim 7, comprising:
the first storage apparatus transmitting the verification request command to at least one of the second storage apparatus and the third storage apparatus at a predetermined timing; and
in response to this verification request command, the second storage apparatus and the third storage apparatus verifying the consistency in the data between the second and third storage apparatuses at a timing related to the predetermined timing.
9. The backup method according to claim 8, wherein the predetermined time concerns an elapsed time from a last transmission of the verification request command.
10. The backup method according to claim 7, wherein:
transmission of the data from the first storage apparatus to the second storage apparatus is conducted using a synchronous method, and transmission of the data from the first storage apparatus to the third storage apparatus is conducted using a synchronous method; and
upon the data consistency verification instructed by the verification request command, if the data stored in the second storage apparatus and the data stored in the third storage apparatus do not match, the data in the third storage apparatus is overwritten with the corresponding data stored in the second storage apparatus.
11. The backup method according to claim 7, comprising the first storage apparatus judging whether or not a failure has occurred in the second storage apparatus or the third storage apparatus, or whether or not a communication link between the second storage apparatus and the third storage apparatus has been cut on a basis of an existence or non-existence of an error in communication between the second storage apparatus and the third storage apparatus.
12. The backup method according to claim 7, wherein:
if a failure occurs in a faulty one of the second storage apparatus and the third storage apparatus, data in a non-faulty one of the second storage apparatus and the third storage apparatus is transmitted to the faulty storage apparatus after recovery of the faulty storage apparatus; and
the faulty storage apparatus is recovered by storing the data transmitted from the other storage apparatus.
13. A storage system comprising:
a first storage apparatus located at a first site;
a second storage apparatus located at a second site;
a third storage apparatus located at a third site; and
a network connecting the first, second, and third storage apparatuses to one another in a communication-enabling manner,
wherein, the first storage apparatus stores data transmitted from a host system and transmits the data to the second and the third storage apparatuses, and the first storage apparatus transmits a data-comparison verification request command upon the first storage apparatus’ determination that a predetermined number of storage system access requests has occurred or a predetermined time has been exceeded, the first storage apparatus transmitting the data-comparison verification request command to at least one of the second and the third storage apparatuses to instruct that a data-comparison consistency verification be conducted between the data stored in the second and the third storage apparatuses; and
wherein the second and the third storage apparatuses individually store the data transmitted from the first storage apparatus, and
wherein at least one of the second and the third storage apparatuses are adapted to perform data-comparison consistency verification operations responsive to the data-comparison verification request command issued from the first storage apparatus, to compare and verify the consistency in the data between the second and third storage apparatuses, wherein the first storage apparatus does not perform any of the data-comparison consistency verification operations to compare and verify the consistency in the data between the second and third storage apparatuses.
14. The storage system according to claim 13, wherein:
transmission of the data from the first storage apparatus to the second storage apparatus is conducted using a synchronous method;
transmission of the data from the first storage apparatus to the third storage apparatus is conducted using a synchronous method; and
upon the data-comparison consistency verification instructed by the data-comparison verification request command, if the data stored in the second storage apparatus and the data stored in the third storage apparatus do not match upon comparison, the data stored in the third storage apparatus is overwritten with the corresponding data stored in the second storage apparatus.
15. The storage system according to claim 13, wherein the first storage apparatus judges whether or not a failure has occurred in the second storage apparatus or the third storage apparatus, or whether or not a communication link between the second and the third storage apparatuses has been cut, on a basis of an existence or non-existence of an error in communication between the second storage apparatus and the third storage apparatus.
16. The storage system according to claim 13, wherein:
when a failure occurs in a faulty one of the second storage apparatus and the third storage apparatus, data in a non-faulty one of the second storage apparatus and third storage apparatus is transmitted to the faulty storage apparatus after recovery of the faulty storage apparatus; and
the faulty storage apparatus is recovered by storing the data transmitted from the other storage apparatus.
17. A backup method for a storage system including: a first storage apparatus located at a first site; a second storage apparatus located at a second site; a third storage apparatus located at a third site, and a network connecting the first, second, and third storage apparatuses to one another in a communication-enabling manner, the method comprising:
the first storage apparatus storing data transmitted from a host system and also transmitting the data to the second storage apparatus and the third storage apparatus, and the first storage apparatus transmitting a data-comparison verification request command issued by the first storage apparatus upon the first storage apparatus’ determination that a predetermined number of storage system access requests has occurred or a predetermined time has been exceeded, the first storage apparatus transmitting the data-comparison verification request command to at least one of the second and the third storage apparatuses to instruct that a data-comparison consistency verification be conducted between the data stored in the second and the third storage apparatuses;
the second storage apparatus and the third storage apparatus storing, individually, the data transmitted from the first storage apparatus, and
at least one of the second and the third storage apparatuses performing data-comparison consistency verification operations for comparing and verifying a consistency in the data between the second and third storage apparatuses responsive to the data-comparison verification request command issued from the first storage apparatus, wherein the first storage apparatus does not perform any of the data-comparison consistency verification operations to compare and verify the consistency in the data between the second and third storage apparatuses.
18. The backup method according to claim 17, wherein:
transmission of the data from the first storage apparatus to the second storage apparatus is conducted using a synchronous method, and transmission of the data from the first storage apparatus to the third storage apparatus is conducted using a synchronous method; and
upon the data-comparison consistency verification instructed by the data-comparison verification request command, if the data stored in the second storage apparatus and the data stored in the third storage apparatus do not match upon comparison, the data in the third storage apparatus is overwritten with the corresponding data stored in the second storage apparatus.
19. The backup method according to claim 17, comprising the first storage apparatus judging whether or not a failure has occurred in the second storage apparatus or the third storage apparatus, or whether or not a communication link between the second storage apparatus and the third storage apparatus has been cut on a basis of an existence or non-existence of an error in communication between the second storage apparatus and the third storage apparatus.
20. The backup method according to claim 17, wherein:
if a failure occurs in a faulty one of the second storage apparatus and the third storage apparatus, data in a non-faulty one of the second storage apparatus and the third storage apparatus is transmitted to the faulty storage apparatus after recovery of the faulty storage apparatus; and
the faulty storage apparatus is recovered by storing the data transmitted from the other storage apparatus.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A self-repairable semiconductor, comprising:
a first device implemented by said self-repairable semiconductor;
a replacement device implemented by said self-repairable semiconductor for said first device; and
a switching device implemented by said self-repairable semiconductor that selectively swaps said replacement device for said first device when said first device is non-operable, wherein said switching device includes an analog switching circuit that selects one of a first pair of differential outputs of said first device having a first common mode voltage and a second pair of differential outputs of said replacement device having a second common mode voltage, wherein said analog switching circuit comprises:
first and second switches having first ends that communicate with the first pair of differential outputs;
third and fourth switches having first ends that communicate with the second pair of differential outputs;
an amplifier having a first input that communicates with second ends of said first and third switches and a second input that communicates with second ends of said second and fourth switches; and
a common mode feedback circuit that communicates with said first and second inputs of said amplifier and that maintains a common mode voltage input of said amplifier below the first common mode voltage.
2. The self-repairable semiconductor of claim 1 wherein said first and third switches include first and second transistors, respectively, said first ends are one of drains and sources of said first and second transistors and said second ends are the other of said drains and sources.
3. The self-repairable semiconductor of claim 1 further comprising:
a first pair of resistors that are arranged between the first device and said first and second switches; and
a second pair of resistors that are arranged between the replacement device and said third and fourth switches.
4. The self-repairable semiconductor of claim 1 further comprising:
a first resistance element having a first end that communicates with said first input of said amplifier and a second end that communicates with a first output of said amplifier; and
a second resistance element having a first end that communicates with said second input of said amplifier and a second end that communicates with a second output of said amplifier.
5. The self-repairable semiconductor of claim 1 wherein said common mode feedback circuit includes:
a second amplifier that includes a common mode input, a first input that communicates with said first input of said amplifier, a second input that communicates with said second input of said amplifier, and first and second outputs;
a first current source that communicates with said first input of said amplifier and said first output of said second amplifier, wherein a first current that is output by said first current source is adjusted by said first output of said amplifier; and
a second current source that communicates with said second input of said amplifier and said second output of said second amplifier, wherein a second current that is output by said second current source is adjusted by said second output of said second amplifier.
6. The self-repairable semiconductor of claim 1 further comprising:
a fifth switch that selectively shorts the first pair of differential outputs of the first device; and
a sixth switch that selectively shorts the second pair of differential outputs of the replacement device.
7. The self-repairable semiconductor of claim 6 further comprising:
a first bias circuit that biases the first pair of differential outputs when the first pair of differential outputs are shorted; and
a second bias circuit that biases the second pair of differential outputs when the second pair of differential outputs are shorted.
8. The self-repairable semiconductor of claim 1 further comprising:
a fifth switch that is connected to said first input of said amplifier and said second ends of said first and third switches; and
a sixth switch that is connected to said second input of said amplifier and said second ends of said second and fourth switches.
9. The self-repairable semiconductor of claim 1 wherein said common mode feedback circuit maintains said common mode voltage input of said amplifier below the second common mode voltage.
10. A self-repairable semiconductor, comprising:
first means for providing a first function implemented by said self-repairable semiconductor;
replacement means implemented by said self-repairable semiconductor for selectively replacing said first device; and
switching means implemented by said self-repairable semiconductor for selectively swapping said replacement means for said first means when said first means is non-operable, wherein said switching means includes analog switching means for selecting one of a first pair of differential outputs of said first means having a first common mode voltage and a second pair of differential outputs of said replacement means having a second common mode voltage, wherein said analog switching means comprises:
first and second switching means for switching and having first ends that communicate with the first pair of differential outputs;
third and fourth switching means for switching and having first ends that communicate with the second pair of differential outputs;
first amplifying means for amplifying and having a first input that communicates with second ends of said first and third switching means and a second input that communicates with second ends of said second and fourth switching means; and
feedback means that communicates with said first and second inputs of said first amplifying means for maintaining a common mode voltage input of said first amplifying means below the first common mode voltage.
11. The self-repairable semiconductor of claim 10 wherein said first and third switching means include first and second transistors, respectively, said first ends are one of drains and sources of said first and second transistors, and said second ends are the other of said drains and sources.
12. The self-repairable semiconductor of claim 10 further comprising:
a first pair of resistors that are arranged between the first means and said first and second switching means; and
a second pair of resistors that are arranged between the replacement means and said third and fourth switching means.
13. The self-repairable semiconductor of claim 10 further comprising:
first resistance means for providing resistance and having a first end that communicates with said first input of said first amplifying means and a second end that communicates with a first output of said first amplifying means; and
second resistance means for providing a resistance and having a first end that communicates with a second input of said first amplifying means and a second end that communicates with said second output of said first amplifying means.
14. The self-repairable semiconductor of claim 10 wherein said common mode feedback circuit includes:
second amplifying means for amplifying and that includes a common mode input, a first input that communicates with said first input of said first amplifying means, a second input that communicates with said second input of said first amplifying means, and first and second outputs;
first current means for providing a first current and for communicating with said first input of said first amplifying means and said first output of said second amplifying means, wherein said first current that is output by said first current means is adjusted by said first output of said second amplifying means; and
second current means for providing a second current and for communicating with said second input of said first amplifying means and said second output of said second amplifying means, wherein said second current that is output by said second current means is adjusted by said second output of said second amplifying means.
15. The self-repairable semiconductor of claim 10 further comprising:
fifth switching means for selectively shorting the first pair of differential outputs of the first means; and
sixth switching means for selectively shorting the second pair of differential outputs of the replacement means.
16. The self-repairable semiconductor of claim 15 further comprising:
first bias means for biasing the first pair of differential outputs when the first pair of differential outputs are shorted; and
second bias means for biasing the second pair of differential outputs when the second pair of differential outputs are shorted.
17. The self-repairable semiconductor of claim 10 further comprising:
first gain error reducing means that is connected to said first input of said amplifying means and said second ends of said first and third switching means for reducing gain error; and
second gain error reducing means that is connected to said second input of said amplifying means and said second ends of said second and fourth switching means for reducing gain error.
18. The self-repairable semiconductor of claim 10 wherein said feedback means maintains said common mode voltage input of said first amplifying means below the second common mode voltage.
19. A method for operating a self-repairable semiconductor, comprising:
implementing a first device, a replacement device and a switching device using said self-repairable semiconductor;
selectively swapping said replacement device for said first device when said first device is non-operable, wherein said selectively swapping includes:
providing an analog switching circuit that selects one of a first pair of differential outputs of the first device having a first common mode voltage and a second pair of differential outputs of the replacement device having a second common mode voltage;
selecting the one of said first and second pair of differential outputs to an amplifier; and
maintaining a common mode voltage input of said amplifier below the first common mode voltage.
20. The method of claim 19 further comprising selectively shorting the other one of the first and second pairs of differential outputs of the first device.
21. The method of claim 20 further comprising biasing said other one of the first and second pairs of differential outputs when said other one of the first and second pairs of differential outputs is shorted.
22. The method of claim 19 further comprising maintaining said common mode voltage input of said amplifier below the second common mode voltage.