1. A spindle motor for use in a disk drive apparatus to drive a disk, the disk drive apparatus including a housing defining an interior space, the spindle motor comprising:
a stationary portion including a shaft which extends in an axial direction;
a base portion configured to define a portion of the housing, and including a through hole into which the shaft is inserted; and
a rotating portion configured to rotate about a central axis with respect to the stationary portion through a bearing mechanism; wherein
the shaft includes:
a non-through hole portion extending downward from an upper end of the shaft;
a first connection channel extending from the hole portion in a radial direction to connect the hole portion with an interior of the bearing mechanism; and
a second connection channel extending from the hole portion in the radial direction to connect the hole portion with a space defined on a lower side of the bearing mechanism; wherein
an upper portion of the hole portion includes a screw hole portion including a screw thread;
a minimum diameter of the screw thread is greater than an inside diameter of the hole portion;
a sealing member is positioned between the screw hole portion and the first connection channel; and
the interior space, the second connection channel, the hole portion, and the first connection channel together define a continuous space.
2. The spindle motor according to claim 1, wherein the sealing member is fixed to an inner surface of the hole portion through an adhesive.
3. The spindle motor according to claim 1, wherein
the sealing member is made of an elastic material;
an outside diameter of the sealing member is greater than the inside diameter of the hole portion; and
the sealing member is located in the hole portion.
4. The spindle motor according to claim 2, wherein the sealing member is in a shape of a ball.
5. The spindle motor according to claim 1, wherein
the shaft is made of stainless steel;
the sealing member is made of a metallic material softer than the stainless steel;
an outside diameter of the sealing member is greater than the inside diameter of the hole portion; and
the sealing member is located in the hole portion.
6. The spindle motor according to claim 1, wherein
the shaft includes an intermediate portion located between the hole portion and the screw hole portion;
an inside diameter of the intermediate portion is greater than the inside diameter of the hole portion and smaller than the minimum diameter of the screw thread; and
the sealing member is located in the intermediate portion.
7. The spindle motor according to claim 6, wherein the sealing member is fixed to an inner surface of the intermediate portion through an adhesive.
8. The spindle motor according to claim 1, wherein
the second connection channel is located between a first cover member located on the lower side of the bearing mechanism and an inner circumferential portion arranged to define a through hole; and
an opening portion located radially outside of the second connection channel does not radially overlap with the first cover member or the inner circumferential portion.
9. The spindle motor according to claim 1, wherein
the base portion includes an inner circumferential portion defining the through hole, the inner circumferential portion and a lower portion of the shaft defining a press-fitting region therebetween; and
an axial extension range of the hole portion is arranged so as not to overlap with the press-fitting region.
10. The spindle motor according to claim 9, wherein an axial length of the hole portion is greater than an axial length of a solid region which does not include a through hole defined on a lower side of the hole portion.
11. The spindle motor according to claim 1, wherein
the base portion includes an inner circumferential portion defining the through hole, the inner circumferential portion and a lower portion of the shaft defining a press-fitting region therebetween; and
an axial length of a range over which an axial extension range of the hole portion and the press-fitting region overlap with each other is about half or less than half an axial length of the press-fitting region.
12. The spindle motor according to claim 11, wherein an axial length of the hole portion is greater than an axial length of a solid region which does not include a through hole defined on a lower side of the hole portion.
13. A disk drive apparatus comprising:
the spindle motor of claim 1 configured to rotate a disk;
an access portion configured to perform at least one of reading and writing of information from or to the disk;
a clamper configured to clamp the disk to the spindle motor; and
a housing configured to contain the disk, the spindle motor, the access portion, and the clamper.
14. The disk drive apparatus according to claim 13, wherein
the housing includes a housing member configured to cover an upper side of the spindle motor; and
the housing member and the shaft are fixed to each other through a screw inserted into the screw hole portion.
15. The disk drive apparatus according to claim 14, further comprising a sealant located at all circumferential positions between the screw hole portion and the screw, or at all circumferential positions between the housing member and a head portion of the screw.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A nonvolatile semiconductor memory device comprising:
first and second bit lines;
first and second word lines;
first and second select transistors;
a source line;
a plurality of memory cells including first, second and third memory cells, each memory cell capable of storing n bits of data (n is a natural number equal to or larger than two), the first memory cell connected to the first word line, coupled to the first bit line and coupled to the source line via the first select transistor, the second memory cell being adjacent to the first memory cell along the first word line, connected to the first word line, coupled to the second bit line and coupled to the source line via the second select transistor, the third memory cell connected to the second word line, coupled to the first bit line and coupled to the source line via the first select transistor and the first memory cell, a source of the third memory cell connected to a drain of the first memory cell; and
a write circuit configured to write a first bit of data into the first memory cell, write a second bit of data into the second memory cell, and write a third bit of data into the third memory cell, before writing a fourth bit of data into the first memory cell without erasing the first bit of data in the first memory cell, wherein:
the write circuit is configured to write the first bit of data into the first memory cell by altering a threshold voltage of the first memory cell from a first voltage to a second voltage according to a first logical state of the first bit of data;
the write circuit is configured to write the fourth bit of data into the first memory cell by altering the threshold voltage of the first memory cell from the second voltage to a third voltage according to a first logical state of the fourth bit of data; and
the write circuit is configured to write the fourth bit of data into the first memory cell by altering the threshold voltage of the first memory cell from the second voltage to a fourth voltage higher than the third voltage according to a second logical state of the fourth bit of data.
2. The semiconductor memory device according to claim 1, wherein the first logical state of the first bit of data is \u201c0\u201d.
3. The semiconductor memory device according to claim 1, wherein:
the first logical state of the fourth bit of data is \u201c0\u201d; and
the second logical state of the fourth bit of data is \u201c1\u201d.
4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a NAND-type flash memory.
5. The semiconductor memory device according to claim 1, wherein:
the write circuit is configured to write the first bit of data into the first memory cell before writing the second bit of data into the second memory cell; and
the write circuit is configured to write the second bit of data into the second memory cell before writing the third bit of data into the third memory cell.
6. The semiconductor memory device according to claim 1, the semiconductor memory device further comprising a third word line, wherein:
the memory cells further include fourth and fifth memory cells;
the fourth memory cell is adjacent to the third memory cell along the second word line, connected to the second word line, coupled to the second bit line and coupled to the source line via the second select transistor and the second memory cell;
the fifth memory cell is connected to the third word line, coupled to the first bit line and coupled to the source line via the first select transistor and the first and third memory cells; and
the write circuit is configured to write a fifth bit of data into the fourth memory cell and write a sixth bit of data into the fifth memory cell before writing a seventh bit of data into the third memory cell without erasing the third bit of data in the third memory cell.
7. The semiconductor memory device according to claim 6, wherein the write circuit is configured to write the fourth bit of data into the first memory cell, write the seventh bit of data into the third memory cell and write an eighth bit of data into the second memory cell, before writing a ninth bit of data into the first memory cell.
8. The semiconductor memory device according to claim 7, wherein:
the write circuit is configured to write the ninth bit of data into the first memory cell by altering the threshold voltage of the first memory cell from the third voltage to a fifth voltage according to a first logical state of the ninth bit of data;
the write circuit is configured to write the ninth bit of data into the first memory cell by altering the threshold voltage of the first memory cell from the third voltage to a sixth voltage according to a second logical state of the ninth bit of data;
the write circuit is configured to write the ninth bit of data into the first memory cell by altering the threshold voltage of the first memory cell from the fourth voltage to a seventh voltage according to a first logical state of the ninth bit of data; and
the write circuit is configured to write the ninth bit of data into the first memory cell by altering the threshold voltage of the first memory cell from the fourth voltage to an eighth voltage according to a second logical state of the ninth bit of data.
9. The semiconductor memory device according to claim 1, wherein:
the write circuit includes a plurality of data storage circuits configured to store data to be written in the memory cells; and
the first and second bit lines are coupled to the same data storage circuit.
10. The semiconductor memory device according to claim 1, wherein the write circuit is configured to write the first bit of data into the first memory cell by maintaining the threshold voltage of the first memory cell at the first voltage according to a second logical state of the first bit of data.
11. The semiconductor memory device according to claim 1, the semiconductor memory device further comprising a plurality of flag cells, wherein:
the write circuit is configured to write flag information indicating that the fourth bit of data has been written into the first memory cell, into one of the flag cells selected concurrently with the first memory cell, when the write circuit writes the fourth bit of data into the first memory cell.