1. A processor, comprising:
a loop counter that is reset to 0 when a loop instruction for executing a process in a loop from a loop start address to a loop end address is issued;
a data memory that receives data that is used for executing a process in the loop, in which the data is transferred from outside;
a calculator that uses the data transferred to said data memory to execute the process in the loop;
a data counter that increments said loop counter by 1 every time a certain amount of data that is used for executing a process in the loop is transferred from the outside to a data memory, wherein said loop counter is only incremented as a result of incrementing of said data counter; and
a loop controller that decrements said loop counter by 1 and causes said calculator to execute the process in the loop when a loop count value of said loop counter is not 0,
wherein, when the loop count value of said loop counter is 0, said loop controller waits until the loop count value of said loop counter becomes 1 or greater, or said loop controller exits the loop when a loop exit condition corresponding to a data transfer completion notification is set.
2. The processor according to claim 1, wherein a data count condition is set in advance to said data counter, and said data counter increments said loop counter by 1 every time a certain amount of data that satisfies the data count condition is transferred from the outside to said data memory.
3. The processor according to claim 2, wherein the data count condition defines a range of a value of data, and
wherein said data counter increments said loop counter by 1 every time a certain amount of data at a value within the range defined by the data count condition is transferred from the outside to said data memory.
4. The processor according to claim 2, wherein the data count condition defines a range of an address of said data memory, and
wherein said data counter increments said loop counter by 1 every time a certain amount of data is transferred to an address within the range defined by the data count condition, from the outside to said data memory.
5. The processor according to claim 1, further comprising:
a program counter that notifies the loop controller of an instruction address of an instruction to be issued.
6. The processor according to claim 5, wherein the program counter sequentially increments the instruction address and notifies the loop controller of the incremented instruction address.
7. The processor according to claim 5, wherein, when the instruction address notified by the program counter coincides with the loop start address, the loop controller determines whether the loop current value notified by loop counter is 0.
8. The processor according to claim 5, wherein, if the loop count value is 0, the loop controller notifies the program counter of the loop start address as an instruction address jump destination.
9. The processor according to claim 5, further comprising:
an instruction memory that received notification from the loop controller of a forced NOP (No Operation) to forcefully issue a NOP instruction.
10. The processor according to claim 9, wherein, if the loop count value is 0, the loop controller notifies the instruction memory of the forced NOP to terminate a program progress until the loop count value becomes 1 or greater.
11. The processor according to claim 9, wherein, if the loop count value is 1 or greater, the loop controller notifies the loop counter of a decrement signal.
12. A method for controlling loop count by a processor, the method comprising:
resetting a loop counter to 0 when a loop instruction for executing a process in a loop from a loop start address to a loop end address is issued;
incrementing said loop counter, by a data counter, by 1 every time a certain amount of data that is used for executing a process in the loop is transferred from outside to a data memory, wherein said loop counter is only incremented as a result of incrementing of said data counter; and
decrementing said loop counter, by a loop controller, by 1 and executing the process in the loop when a loop count value of said loop counter is not 0,
wherein, when the loop count value of said loop counter is 0, said loop controller waits until the loop count value of said loop counter becomes 1 or greater, or said loop controller exits the loop when a loop exit condition corresponding to a data transfer-completion notification is set.
13. The method of loop count control according to claim 12, wherein, in said incrementing said loop counter by 1, said loop counter is incremented by 1 every time a certain amount of data that satisfies a preset data count condition is transferred from the outside to said data memory.
14. The method of loop count control according to claim 13, wherein the data count condition defines a range of a value of data, and
wherein in said incrementing said loop counter by 1, said loop counter is incremented by 1 every time a certain amount of data at a value within the range defined by the data count condition is transferred from the outside to said data memory.
15. The method of loop count control according to claim 13, wherein the data count condition defines a range of an address of said data memory, and
wherein, in said incrementing said loop counter by 1, said loop counter is incremented by 1 every time a certain amount of data is transferred to an address within the range defined by the data count condition, from the outside to said data memory.
16. The method of loop count control according to claim 12, further comprising:
notifying a loop controller that performs said decrementing said loop counter of an instruction address of an instruction to be issued.
17. The method of loop count control according to claim 16, further comprising:
sequentially incrementing the instruction address and notifying the loop controller of the incremented instruction address.
18. The method of loop count control according to claim 16, wherein, when the instruction address coincides with the loop start address, the loop controller determines whether the loop current value is 0.
19. The method of loop count control according to claim 16, further comprising:
receiving, by an instruction memory, notification from the loop controller of a forced NOP (No Operation) to forcefully issue a NOP instruction.
20. The method of loop count control according to claim 19, wherein, if the loop count value is 0, the loop controller notifies the instruction memory of the forced NOP to terminate a program progress until the loop count value becomes 1 or greater.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A DC converter having a transformer including primary and secondary windings that are loosely coupled with each other, a main switch connected in series with the primary winding, and a series circuit connected to ends of one of the primary winding and main switch and including a clamp capacitor and an auxiliary switch, the main and auxiliary switches being alternately turned onoff so that a voltage of the secondary winding of the transformer is synchronously rectified with synchronous rectifiers and is smoothed with smoothing elements to provide a DC output, the DC converter comprising
a tertiary winding provided for the transformer, tightly coupled with the primary winding, and configured to generate a voltage that drives the synchronous rectifiers.
2. A DC converter having a transformer including a primary winding, a first secondary winding very loosely coupled with the primary winding, and a second secondary winding loosely coupled with the primary winding, a main switch connected in series with the primary winding, and a series circuit being connected to ends of one of the primary winding and main switch and including a clamp capacitor and an auxiliary switch, the main and auxiliary switches being alternately turned onoff so that, energy is accumulated in a leakage inductance between the primary winding and the first secondary winding as the main switch is ON, the accumulated energy being transferred through the second secondary winding to a secondary side of the transformer as the main switch is OFF, and a voltage of the secondary windings being synchronously rectified with synchronous rectifiers and smoothed with smoothing elements to provide a DC output, the DC converter comprising
a tertiary winding provided for the transformer, tightly coupled with the primary winding, and configured to generate a voltage that drives the synchronous rectifiers.
3. The DC converter of claim 1, further comprising
a first capacitor connected in series with the tertiary winding of the transformer and configured to drive the synchronous rectifiers through the first capacitor.
4. The DC converter of claim 2, further comprising
a first capacitor connected in series with the tertiary winding of the transformer and configured to drive the synchronous rectifiers through the first capacitor.
5. The DC converter of claim 3, further comprising
a second capacitor connected in parallel with a drive terminal of each of the synchronous rectifiers.
6. The DC converter of claim 4, further comprising
a second capacitor connected in parallel with a drive terminal of each of the synchronous rectifiers.