1. A machine-readable non-transitory storage medium having instructions therein, which when executed by a machine, cause the machine to perform a method, the method comprising:
generating initial inline code from a source code block of a source code, the source code block specifying at least one access to an object, the initial inline code having serial inline cache code to perform the one access to the object, wherein the serial inline cache code includes a serial slow code path and a fast code path, the serial inline cache code embedding one or more parameters to determine whether to perform the one access to the object via the fast code path or the serial slow code path;
generating concurrent inline code from the source code block, the concurrent inline code having concurrent inline cache code to perform the one access to the object, wherein the concurrent inline cache code includes a concurrent slow code path and the fast code path, the concurrent inline cache code embedding the parameters to determine whether to perform the access to the object via the fast code path or the concurrent slow code path;
executing the initial inline code via a particular thread to perform the at least one access to the object, wherein the serial slow code path includes self modifying code to update the parameters of the serial inline cache code; and
executing the concurrent inline code via one or more threads concurrently to perform the at least one access to the object, wherein the concurrent slow code path includes self modifying code to update the parameters of the concurrent inline cache code,
wherein the fast code path is executed to perform the at least one access to the object if the updated parameters of the serial inline cache code or the updated parameters of the concurrent inline cache code correspond to an object type matching a type of the object,
wherein the initial inline code is executed by the particular thread for initialization of the parameters and,
wherein the concurrent inline code is generated subsequent to the execution of the initial inline code.
2. The medium of claim 1, wherein the initial inline code includes guard code to prohibit the one or more threads from executing the serial inline cache code.
3. The medium of claim 2, wherein the initial inline code is generated via the particular thread, and wherein the guard code is to determine whether the initial inline code is executed by the particular thread.
4. The medium of claim 1, wherein the serial slow code path is executed via an interpreter to update the constant parameters for initializing the fast code path and wherein the interpreter invokes a data coherency mechanism among multiple processors to share the initialized fast code path without invoking a instruction coherence mechanism among the multiple processors.
5. The medium of claim 4, wherein the serial slow code path includes table lookup operation to be performed by the interpreter.
6. The medium of claim 4, wherein the concurrent slow code path includes table lookup operation to be performed independent of the interpreter.
7. The medium of claim 1, wherein the parameters of the serial inline cache code are updated via the particular thread before the concurrent inline code is generated, and wherein the concurrent inline cache code are generated according to the updated parameters of the serial inline cache code.
8. The medium of claim 1, wherein the parameters are represented as assembly code constants.
9. The medium of claim 8, wherein a copy of the concurrent inline code is stored in a code buffer and wherein the update of the parameters via the self modifying code comprises:
modifying the copy of the concurrent inline code in the code buffer with the updated parameters, wherein the copy of the concurrent inline code modified asynchronously with the execution of the concurrent inline code among the one or more threads.
10. The medium of claim 9, wherein the concurrent inline code is executed by at least one processor capable of instruction caching, the method further comprising:
flushing instruction caches of the at least one processor via a dedicated thread, wherein the instruction caches are flushed according to a schedule.
11. The medium of claim 10, wherein the concurrent inline code modified with the updated parameters in the code buffer is invoked subsequent to the flushing of the instruction cache to replace the concurrent inline code previously as compiled code for the source code block.
12. The medium of claim 1, wherein the source code is based on a dynamic typed programming language, wherein the object has a dynamic structure associated one or more properties with corresponding property values, and wherein the type of the object corresponds to the dynamic structure.
13. The medium of claim 12, wherein one of the parameters indicates a pointer referencing the dynamic structure of the object, the pointer representing the type of the object.
14. The medium of claim 13, wherein the access to the object includes loading operations for one of the property values via a memory address.
15. The medium of claim 14, wherein the one property value is stored in the memory address and wherein one of the parameters has a value corresponding to an offset to locate the memory address via the dynamic structure.
16. The medium of claim 14, wherein the memory address for the loading operations is determined via a table lookup operation if the pointer in the constant parameters does not refer to the dynamic structure of the object.
17. A machine-readable non-transitory storage medium having instructions therein, which when executed by a machine, cause the machine to perform a method, the method comprising:
generating initial inline code from a source code block of a source code, the source code block specifying at least one access to an object, the initial inline code having serial inline cache code to perform the one access to the object, wherein the serial inline cache code includes a serial slow code path and a fast code path, the serial inline cache code to determine whether to perform the one access to the object via the fast code path or the serial slow code path;
generating concurrent inline code from the source code block, the concurrent inline code having concurrent inline cache code to perform the one access to the object, wherein the concurrent inline cache code includes a concurrent slow code path and the fast code path, the concurrent inline cache code to determine whether to perform the access to the object via the fast code path or the concurrent slow code path;
executing the initial inline code via a particular thread to perform the at least one access to the object, wherein the serial inline cache code embeds one or more constant parameters associated with an object type for the fast code path, wherein the serial slow code path is executed via the particular thread to update values of the constant parameters of the serial inline cache code, wherein the initial inline code is generated via the particular thread and wherein the initial inline code includes guard code to determine whether the initial inline code is executed by the particular thread; and
executing the concurrent inline code via one or more threads to perform the at least one access to the object, wherein the concurrent inline cache code embeds the constant parameters for the fast code path, wherein the concurrent slow code path is executed concurrently to update values of the constant parameters of the concurrent inline cache code, the guard code to prohibit the one or more threads from executing the serial inline cache code, wherein the concurrent inline code is generated via one of the one or more threads as a result of executing the guard code via the one thread to determine that the initial inline code is not being executed by the particular thread,
wherein the fast code path is executed to perform the at least one access to the object if the updated constant parameters of the serial inline cache code or the updated constant parameters of the concurrent inline cache code correspond to an object type matching a type of the object.
18. The medium of claim 17, wherein the concurrent inline code is generated from the initial inline code and wherein the generation of the concurrent inline code comprises:
patching the guard code as a no operation code to allow a thread to perform the concurrent inline cache code independent of an identity of the thread.
19. A machine-readable non-transitory storage medium having instructions therein, which when executed by a machine, cause the machine to perform a method, the method comprising:
compiling a serial inline cache code for a function via an initial thread, the function specified in a source code for accessing an object, wherein the serial inline cache code includes a serial slow code path and a fast code path, the serial slow code path to perform the access of the object via table lookup operations, the fast code path to perform the access of the object via direct memory loading operations via a memory address embedded in the fast code path, the serial slow code path including self modifying code to update the memory address;
executing the serial slow code path to access the object via an interpreter by the initial thread, wherein the memory address of the fast code path is initialized via the self modifying code in the execution of the serial slow code path;
in response to a call to the function via a thread separate from the initial thread, compiling a concurrent inline cache code for the function, the concurrent inline cache code including the fast code path having the memory address initialized via the execution of the serial slow code path, the concurrent inline cache code having a concurrent slow code path for the access of the object via the table lookup operations, the concurrent inline cache code to determine whether to perform the access to the object via the concurrent slow code path or the fast code path; and
executing the concurrent inline cache code via one or more threads to perform the function without invoking the interpreter, wherein the memory address of the fast code path is reinitialized if the concurrent slow code path of the concurrent inline cache code is executed.
20. A computer including a memory and one or more hardware processors, the hardware processors executing instructions stored in the memory, the hardware processors configured to perform a method comprising:
generating initial inline code from a source code block of a source code, the source code block specifying at least one access to an object, the initial inline code having serial inline cache code to perform the one access to the object, wherein the serial inline cache code includes a serial slow code path and a fast code path, the serial inline cache code embedding one or more parameters to determine whether to perform the one access to the object via the fast code path or the serial slow code path;
generating concurrent inline code from the source code block, the concurrent inline code having concurrent inline cache code to perform the one access to the object, wherein the concurrent inline cache code includes a concurrent slow code path and the fast code path, the concurrent inline cache code embedding the parameters to determine whether to perform the access to the object via the fast code path or the concurrent slow code path;
executing the initial inline code via a particular thread to perform the at least one access to the object, wherein the serial slow code path includes self modifying code to update the parameters of the serial inline cache code;
executing the concurrent inline code via one or more threads concurrently to perform the at least one access to the object, wherein the concurrent slow code path includes self modifying code to update the parameters of the concurrent inline cache code; and
executing the fast code path to perform the at least one access to the object if the updated parameters of the serial inline cache code or the updated parameters of the concurrent inline cache code represents an updated object type matching a type of the object,
wherein the initial inline code is executed by the particular thread for initialization of the parameters and,
wherein the concurrent inline code is generated subsequent to the execution of the initial inline code.
21. A computer system comprising:
a memory storing instructions and a source code to perform a data processing task, the source code include a source code block specifying at least one access to an object; and
a processor coupled to the memory to execute the instructions from the memory, the processor being configured to
generate initial inline code from the source code block, the initial inline code having serial inline cache code to perform the one access to the object, wherein the serial inline cache code includes a serial slow code path and a fast code path, the serial inline cache code embedding one or more parameters to determine whether to perform the one access to the object via the fast code path or the serial slow code path,
generate concurrent inline code from the source code block, the concurrent inline code having concurrent inline cache code to perform the one access to the object, wherein the concurrent inline cache code includes a concurrent slow code path and the fast code path, the concurrent inline cache code embedding the parameters to determine whether to perform the access to the object via the fast code path or the concurrent slow code path,
execute the initial inline code via a particular thread to perform the at least one access to the object, wherein the serial slow code path includes self modifying code to update the of the serial inline cache code,
execute the concurrent inline code via one or more threads concurrently to perform the at least one access to the object, wherein the concurrent slow code path includes self modifying code to update the parameters of the concurrent inline cache code, and
execute the fast code path to perform the at least one access to the object if the updated parameters of the serial inline cache code or the updated parameters of the concurrent inline cache code represents an updated object type matching a type of the object,
wherein the initial inline code is executed by the particular thread for initialization of the parameters and,
wherein the concurrent inline code is generated subsequent to the execution of the initial inline code.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor module, comprising:
an insulating layer;
a first electrode provided on a surface of said insulating layer;
a second electrode provided on the other surface of said insulating layer; and
a bump electrically connected with said second electrode by penetrating said insulating layer, said bump being provided integrally with said first electrode,
wherein said bump has a plastic region on a tip part thereof and the plastic region is plastic deformed and connected with said second electrode.
2. A semiconductor module according to claim 1, wherein said bump and said second electrode are made of a same metal.
3. A semiconductor module according to claim 1, wherein said first electrode and said bump are formed using a rolled metal.
4. A semiconductor module according to claim 1, wherein the plastic region includes fine asperities formed on the tip part of said bump.
5. A semiconductor module according to claim 1, wherein the plastic region is made of metal which is more plastic-deformable than portions except for the plastic region of the bump.
6. A semiconductor module according to claim 5, wherein the plastic region is made of gold.
7. A semiconductor module according to claim 1, wherein the tip part of said bump is of a reversed mesa structure realized by a plastic deformation of the plastic region.
8. A mobile apparatus which mounts a semiconductor module according to claim 1.
9. A method for manufacturing a semiconductor module, the method comprising:
a first process of preparing a semiconductor substrate having an electrode on a surface thereof;
a second process of forming a metal sheet with which a bump having a plastic region on a tip thereof is provided integrally; and
a third process of press-bonding the metal sheet and the semiconductor substrate by way of an insulating layer and electrically connecting the bump with the electrode in a manner such that the bump penetrates the insulating layer and the plastic region is plastic deformed.
10. A method for manufacturing a semiconductor module according to claim 9, wherein, in said second process, after forming fine asperities on one surface of a plate-like metal as the plastic region, the bump is formed by selectively removing the one surface thereof.
11. A method for manufacturing a semiconductor module according to claim 9, wherein, in said second process, after the bump is formed by selectively removing one surface of a plate-like metal, fine asperities are formed on the tip portion of the bump as the plastic region.
12. A method for manufacturing a semiconductor module according to claim 9, wherein, in said second process the plastic region is formed by an electrolytic plating method or electroless plating method using gold.
13. A method for manufacturing a semiconductor module according to claim 9, wherein in said second process a shape of the bump is formed in a manner such that the closer to a tip part thereof, the smaller a diameter thereof becomes, and
wherein in said third process the tip part of said bump is plastic deformed so that it has a reversed mesa structure.