1. A method of forming a non-volatile memory array, high-voltage circuits and logic circuits on a substrate, the array overlying a first region of the substrate, the high-voltage circuits overlying a second region of the substrate and the logic circuits overlying a third region of the substrate, comprising:
forming a first dielectric layer that extends across the first, second and third regions;
forming a floating gate polysilicon layer that extends over the first dielectric layer across the first, second and third regions;
forming an inter-layer dielectric layer that extends directly over the floating gate polysilicon layer across the first, second and third regions;
forming a mask layer that extends over the inter-layer dielectric layer across the first, second and third regions;
subsequently forming a plurality of shallow trench isolation structures that extend into the substrate and that separate portions of the floating gate polysilicon layer; and
subsequently removing portions of the floating gate polysilicon layer and portions of the mask layer overlying the second and third regions of the substrate without removing portions of the floating gate polysilicon layer and portions of the mask layer that overlie the first region.
2. The method of claim 1 further comprising subsequently forming a second dielectric layer overlying the second and third regions of the substrate.
3. The method of claim 2 further comprising removing the second dielectric layer overlying the third region and forming a third dielectric layer overlying the third region.
4. The method of claim 3 further comprising removing mask layer portions from the first region and subsequently forming a control-gate polysilicon layer and a control-gate tungsten silicide layer over the first region.
5. The method of claim 1 wherein the inter-layer dielectric layer is an oxide-nitride-oxide (ONO) layer.
6. The method of claim 1 further comprising forming shallow trench isolation structures at interfaces between adjacent regions of the substrate.
7. A method of forming a non-volatile memory array in an array region of a substrate, the non-volatile memory having floating gates that are self-aligned to shallow trench isolation portions and forming peripheral circuits that extend over a high-voltage region and a low-voltage region of the surface of a substrate, comprising:
forming a floating gate dielectric layer of a first thickness that extends over the array region, high-voltage region and low-voltage region;
forming one or more layers of floating gate material that extend directly over the floating gate dielectric layer in the array region, high-voltage region and low-voltage region;
forming an inter-layer dielectric layer that extends directly over the one or more layers of floating gate material in the array region, high-voltage region and low-voltage region;
forming a patterned layer of etch mask material that extends over the inter-layer dielectric layer in the array region, high-voltage region and low-voltage region;
subsequently forming shallow trench isolation structures in the substrate surface in a pattern defined by the etch mask material, thereby dividing the one or more floating gate layers and defining an extent of a floating gate along a first direction;
subsequently removing portions of the floating gate dielectric layer, the one or more layers of floating gate material, the inter-layer dielectric layer and the layer of etch mask material that extend over the high-voltage and low-voltage regions;
subsequently forming a low-voltage dielectric layer of a second thickness over the low-voltage region and a high-voltage dielectric layer of a third thickness over the high-voltage region; and
subsequently forming a control gate layer directly overlying the inter-layer dielectric in the array region, directly overlying the low-voltage dielectric layer in the low-voltage region and directly overlying the high-voltage dielectric layer in the high-voltage region.
8. The method of claim 7 wherein the etch mask material is silicon nitride and the inter-layer dielectric layer is comprised of silicon dioxide on silicon nitride on silicon dioxide.
9. The method of claim 7 wherein the control gate layer consists of polysilicon and tungsten silicide.
10. The method of claim 7 wherein the one or more layers of floating gate material consists of two separately deposited layers of polysilicon.
11. The method of claim 7 wherein the layer of etch mask material is formed of silicon nitride.
12. The method of claim 7 wherein the first thickness is approximately 83 Angstroms, the second thickness is approximately 40 Angstroms and the third thickness is approximately 400 Angstroms.
13. A method of forming a non-volatile memory array, high-voltage circuits and logic circuits on a substrate, the array overlying a first region of the substrate, the high-voltage circuits overlying a second region of the substrate and the logic circuits overlying a third region of the substrate, comprising:
forming a first dielectric layer that extends across the first, second and third regions;
forming a floating gate polysilicon layer that extends over the first dielectric layer across the first, second and third regions;
forming an inter-layer dielectric layer that extends directly over the floating gate polysilicon layer across the first, second and third regions;
forming a mask layer that extends over the inter-layer dielectric layer across the first, second and third regions;
subsequently forming a plurality of shallow trench isolation structures that extend into the substrate and that separate portions of the floating gate polysilicon layer;
subsequently removing portions of the first dielectric layer, portions of the floating gate polysilicon layer and portions of the mask layer overlying the second and third regions of the surface without removing portions of the first dielectric layer, portions of the floating gate polysilicon layer and portions of the mask layer that overlie the first region; and
subsequently forming a second dielectric layer overlying the second region and forming a third dielectric layer overlying the third region.
14. The method of claim 13 further comprising, subsequent to forming the second dielectric layer and the third dielectric layer, forming a control gate layer overlying the first, second and third regions.
15. The method of claim 14 wherein the control gate layer directly overlies the inter-layer dielectric layer over the first region, the control gate layer directly overlies the second dielectric layer over the second region and the control gate layer directly overlies the third dielectric layer over the third region.
16. The method of claim 14 wherein the control gate layer is formed of polysilicon and a metal silicide.
17. The method of claim 13 wherein the second dielectric layer is formed overlying the second and third regions and is later removed from the third region prior to formation of the third dielectric layer.
18. The method of claim 13 wherein the first dielectric layer is thinner than the second dielectric layer and the first dielectric layer is thicker than the third dielectric layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An electronic-device-implemented method for extracting textual information from a document, comprising:
launching an imaging application that executes on the electronic device;
displaying, in a window associated with the imaging application, visual suitability indicators of a tilt orientation of the electronic device relative to a plane of the document;
modifying the visual suitability indicators when the tilt orientation falls within a predefined range;
acquiring an image of the document, after the tilt orientation falls within the predefined range for more than a time interval, using an imaging device, which is integrated into the electronic device; and
extracting the textual information from the image of the document using optical character recognition.
2. The method of claim 1, wherein the method further comprises receiving a user command to extract the textual information; and
wherein the imaging application is launched in response to the user command.
3. The method of claim 1, wherein the visual suitability indicators are non-textual.
4. The method of claim 1, wherein the visual suitability indicators include: a circle in the center of the window, a ball whose position in the window indicates the tilt orientation, and corner markers proximate to the corners of the window.
5. The method of claim 4, wherein the ball is displayed within the circle when the tilt orientation is within the predefined range.
6. The method of claim 1, wherein modifying the visual suitability indicators includes changing color of a visual suitability indicator.
7. The method of claim 1, wherein the image is acquired without the user activating an acquisition icon associated with the imaging device.
8. The method of claim 1, wherein, after acquiring the image, the method further comprises:
displaying the image to a user;
receiving user feedback about the image from a user; and
if the user feedback rejects the image, repeating the displaying, modifying and acquiring operations to acquire another image of the document.
9. The method of claim 1, wherein, after extracting the textual information, the method further comprises receiving user feedback from a user about the accuracy of the extracted textual information.
10. The method of claim 1, wherein the visual suitability indicators further indicate at least one of: light intensity, an in-plane orientation of the document relative to the electronic device, and framing of the document in the window; and
wherein the visual suitability indicators are further modified when at least one of: the light intensity is sufficient, the in-plane orientation falls within a second predefined range, and the document is suitably framed in the window.
11. A computer-program product for use in conjunction with an electronic device, the computer-program product comprising a non-transitory computer-readable storage medium and a computer-program mechanism embedded therein, to extract textual information from a document, the computer-program mechanism including:
instructions for launching an imaging application that executes on the electronic device;
instructions for displaying, in a window associated with the imaging application, visual suitability indicators of a tilt orientation of the electronic device relative to a plane of the document;
instructions for modifying the visual suitability indicators when the tilt orientation falls within a predefined range;
instructions for acquiring an image of the document, after the tilt orientation falls within the predefined range for more than a time interval, using an imaging device, which is integrated into the electronic device; and
instructions for extracting the textual information from the image of the document using optical character recognition.
12. The computer-program product of claim 11, wherein the visual suitability indicators are non-textual.
13. The computer-program product of claim 11, wherein the visual suitability indicators include: a circle in the center of the window, a ball whose position in the window indicates the tilt orientation, and corner markers proximate to the corners of the window.
14. The computer-program product of claim 13, wherein the ball is displayed within the circle when the tilt orientation falls within the predefined range.
15. The computer-program product of claim 11, wherein the visual suitability indicators further indicate at least one of: light intensity, an in-plane orientation of the document relative to the electronic device, and framing of the document in the window; and
wherein the visual suitability indicators are further modified when at least one of: the light intensity is sufficient, the in-plane orientation falls within a second predefined range, and the document is suitably framed in the window.
16. An electronic device, comprising:
a processor;
memory; and
a program module, wherein the program module is stored in the memory and configurable to be executed by the processor to extract textual information from a document, the program module including:
instructions for launching an imaging application that executes on the electronic device;
instructions for displaying, in a window associated with the imaging application, visual suitability indicators of a tilt orientation of the electronic device relative to a plane of the document;
instructions for modifying the visual suitability indicators when the tilt orientation falls within a predefined range;
instructions for acquiring an image of the document, after the tilt orientation falls within the predefined range for more than a time interval, using an imaging device, which is integrated into the electronic device; and
instructions for extracting the textual information from the image of the document using optical character recognition.
17. The electronic device of claim 16, wherein the visual suitability indicators include: a circle in the center of the window, a ball whose position in the window indicates the tilt orientation, and corner markers proximate to the corners of the window.
18. The electronic device of claim 17, wherein the ball is displayed within the circle when the tilt orientation falls within the predefined range.
19. The electronic device of claim 16, wherein the visual suitability indicators further indicate at least one of: light intensity, an in-plane orientation of the document relative to the electronic device, and framing of the document in the window; and
wherein the visual suitability indicators are further modified when at least one of: the light intensity is sufficient, the in-plane orientation falls within a second predefined range, and the document is suitably framed in the window.