1. A system for connecting a first structural panel and a second structural panel comprising:
a first anchor configured to be mounted in a T shaped slot formed in said first structural panel, said first anchor comprising an elongate body defining a plurality of slots separated by one or more mounts;
a second anchor configured to be mounted in a T shaped slot formed in a second structural panel, said second anchor comprising an elongate body defining a plurality of slots separated by one or more mounts; and
a elongate connector, said connector comprising a body having a first side and a second side, at least one first projection extending outwardly from said first side of said body and having an adjacent first slot, said first projection configured to pass into said T shaped slot in said first structural panel and through one of said slots in said first anchor, a least one second projection extending outwardly from said second side of said body and having an adjacent second slot, said second projection configured to pass into said T shaped slot in said second structural panel and through one of said slots in said second anchor, whereby when said connector is moved relative to said first and second anchor, at least one mount of said first anchor moves into a corresponding first slot in said elongate connector adjacent to at least one first projection and at least one mount of said second anchor moves into a corresponding second slot in said elongate connector adjacent to at least one second projection and lateral movement of said first and second anchors relative to said connector is prevented.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A module unit of a logic emulation processor comprising:
one or more than one unit combination circuit processor having a plurality of input signals and a plurality of output signals and operating to emulate an AND-OR converted combination circuit model or memory model;
a plurality of control processors each having a plurality of input signals and one or more than one output signal and operating to generate said input signals of said unit combination circuit processor and emulate a sequential circuit model; and
a plurality of multiplexers each receiving said output signals of said unit combination circuit processors, selecting a signal in demand of a control processor, and delivering the selected signal to said control processor.
2. A module unit of a logic emulation processor according to claim 1, wherein said unit combination circuit processor includes a function control memory which stores operation codes indicative of AND or OR operations and operation operands, and a combination circuit evaluation unit which simulates the AND operation of said AND-OR converted combination circuit for said output signal of said control processor based on the entry of a value of operation code indicative of logical AND and a value of operand and simulates the OR operation of said AND-OR converted combination circuit for said output signal of said control processor based on the entry of a value of operation code indicative of logical OR and a value of operand.
3. A module unit of a logic emulation processor according to claim 2, wherein said operand includes information for directing as to whether or not the input signal of said combination circuit evaluation unit is to be validated and whether or not said signal is to be inverted.
4. A module unit of a logic emulation processor according to claim 1, wherein said unit combination circuit processor includes an interconnecting switch for interconnecting said unit combination circuit processors.
5. A module unit of a logic emulation processor according to claim 4, wherein said combination circuit processor includes an input selector which selects one of multiple sets of outputs of said control processors, and a constructional control memory which stores construction codes indicative of different interconnections of said unit combination circuit processors based on which said input selector selects one of said multiple sets of outputs.
6. A module unit of a logic emulation processor according to claim 1, wherein said unit combination circuit processor includes a memory which receives the output signals of said control processor as input data, write or read address and write enable signal and releases output data as output of said unit combination circuit processor.
7. A module unit of a logic emulation processor according to claim 2, wherein said function control memory is designed to emulate a memory device and said function control memory receives the output signals from said control processor as input data, write or read address and write enable signal and releases output data as output of said unit combination circuit processor.
8. A module unit of a logic emulation processor according to claim 6 including an operation code memory which stores operation codes indicative of the width and depth of said memory, said data being written or read out in accordance with a data width specified by a code which is read out of said operation code memory.
9. A logic emulation processor comprising:
module units interconnected in said logic emulation processor, each of which includes one or more than one unit combination circuit processor having a plurality of input signals and a plurality of output signals and emulating a combination circuit model or memory model, a plurality of control processors each having a plurality of input signals and one or more than one output signal and operating to generate said input signals to said unit combination circuit processor and emulate a sequential circuit model, and a plurality of multiplexers each receiving said output signals of said unit combination circuit processor, selecting a signal in demand of a control processor, and delivering the selected signal to said control processor;
means for interconnecting said module units of M in number based on a complete network; and
means for grouping signals to be transferred among said module units into a maximum of M-1 sets of signals and transferring said divided signal sets via a plurality of paths through the neighboring module units.
10. A logic emulation processor comprising:
module units interconnected in said logic emulation processor, each of which includes one or more than one unit combination circuit processor having a plurality of input signals and a plurality of output signals and emulating a combination circuit model or memory model, a plurality of control processors each having a plurality of input signals and one or more than one output signal and operating to generate said input signals to said unit combination circuit processor and emulate a sequential circuit model, and a plurality of multiplexers each receiving said output signals of said unit combination circuit processor, selecting a signal in demand of a control processor, and delivering the selected signal to said control processor;
means for connecting one of said module unit to other neighboring module units of N in number through buses based on an N-dimensional hypercube; and
means for grouping signals to be transferred among said module units into a maximum of N sets of signals, implementing a first procedure of determining immediate transfer paths of N in number from a message sending module having a node address of PPn1Pn2 . . . P1P0 to a message receiving module having a node address of DDn1Dn2 . . . D1D0 (the node address is a unique binary number given to each module unit) by inverting the node address P at one bit position at a time thereby to obtain Qn1(not Pn1) Pn2 . . . P1P0, Qn2Pn1 (not Pn2 . . . P1P0, . . . , Q1Pn1Pn2 . . . (not P1)P0, and Q0Pn1Pn2 . . . P1 (not P0), implementing a second procedure of taking exclusive logical sums between Qn1 through Q0 and D for individual bits thereby to obtain Rn1 through R0, implementing a third procedure, which is repeatedly for values of i of n1 through 0, of inverting Qi at a same bit position as Ri having a value of 1 sequentially by scanning through the bits downward from the (i1) th bit position of Ri (from the (n1)th bit position in the case of i1) thereby to determine a path from Qi to D, and transferring said divided signal sets from P to D by using the determined paths of N in number.