1. An optical pickup device comprising:
a laser light source;
an objective lens that converges a laser beam emitted from the laser light source, upon an optical disc;
a beam-dividing element that divides a signal beam reflected from the optical disc, into a plurality of beams; and
a photodetector including a plurality of light-receiving surfaces each formed to receive a part of the signal beams obtained by the division;
wherein:
the beam-dividing element divides the reflected signal beam into at least two beams of light, one thereof including a push-pull signal region and one not including the push-pull signal region;
the photodetector detects, of all the signal beams obtained by the division, a beam present in a beam-peripheral region free of the beam including the push-pull signal region;
a detection signal obtained from the beam present in the beam-peripheral region is used to output a source signal for generating a DPD signal that acts as a tracking error signal; and
a signal terminal that outputs a source signal for generating a lens error signal is capable of outputting a source signal for generating a DPD signal detected from the beam present in the beam-peripheral region.
2. The optical pickup device according to claim 1, further comprising:
an interface configured with at least 12 signal terminals;
wherein the 12 signal terminals include:
two signal terminals that output a source signal for generating a push-pull signal;
four signal terminals that output a lens error signal component and DPD signal component with a push-pull signal component excluded;
four signal terminals that output a source signal for generating a focusing error signal; and
two signal terminals that output a source signal for generating an information reproduction signal.
3. The optical pickup device according to claim 1, wherein:
the photodetector is assigned a gain level to use a current-voltage conversion amplifier to amplify signal levels of signals detected on each light-receiving surface, and in order to generate an information reproduction signal, to conduct signal attenuation when a summing operational amplifier conducts an adding operation upon detection signals obtained after the signal amplification with the current-voltage conversion amplifier.
4. The optical pickup device according to claim 1, further including:
a function that reproduces various information signals recorded on a plurality of recording layers provided at a predetermined pitch on the optical disc, and a function that records each of the information signals on each of the recording layers.
5. An optical disc apparatus comprising:
the optical pickup device according to claim 1;
a laser activation circuit that drives the laser light source within the optical pickup device;
a servo signal generating circuit that generates a focusing error signal and a tracking error signal from signals detected from the photodetector within the optical pickup device; and
an information signal reproducing circuit that reproduces an information signal recorded on an optical disc.
6. The optical disc apparatus according to claim 5, further including:
a function that reproduces various information signals recorded on a plurality of recording layers provided at a predetermined pitch on the optical disc, and a function that records each of the information signals on each of the recording layers.
7. An optical pickup device comprising:
a laser light source;
an objective lens that converges a laser beam emitted from the laser light source, upon an optical disc;
a beam-dividing element that divides a signal beam reflected from the optical disc, into a plurality of beams; and
a photodetector including a plurality of light-receiving surfaces each formed to receive a part of the signal beams obtained by the division;
wherein:
the beam-dividing element divides the reflected signal beam into at least two beams of light, one thereof including a push-pull signal region and one not including the push-pull signal region;
the photodetector detects, of all the signal beams obtained by the division, a beam present in a beam-peripheral region free of the beam including the push-pull signal region;
a detection signal obtained from the beam present in the beam-peripheral region is used to output a source signal for generating a DPD signal that acts as a tracking error signal; and
the optical pickup device being of a three-wave compatible type adapted to record information upon and reproduce information from three kinds of media (first, second, and third kinds of media) that differ from one another in wavelength of light,
the three-wave compatible optical pickup device comprising:
a predetermined optical system configuration for recording information upon or reproducing information from the second and third kinds of media; and
an interface configured with a plurality of signal terminal groups concerned with information recording upon and reproduction from the second and third kinds of media;
wherein:
a first signal terminal group in the interface configuration includes signal terminals formed to, during information recording upon or reproduction from the first kind of medium, output a source signal for generating the DPD signal detected from the beam present in the beam-peripheral region;
a second signal terminal group in the interface configuration includes signal terminals formed to, during information recording upon or reproduction from the second and third kinds of media, output a source signal for generating a DPD signal:
a third signal terminal group in the interface configuration includes signal terminals formed to, during information recording upon or reproduction from the first kind of medium, output a source signal for generating a focusing error signal; and
a fourth signal terminal group in the interface configuration includes signal terminals formed to, during information recording upon or reproduction from the second and third kinds of media, output a source signal for generating a subsidiary push-pull signal;
the first signal terminal group being shared with the second signal terminal group, and the third signal terminal group being shared with the fourth signal terminal group.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A semiconductor memory device comprising:
a plurality of folded-type bit-line pairs arranged in parallel to each other;
a plurality of word lines orthogonal to said plurality of bit-line pairs; and
dynamic memory cells each composed of one transistor and one capacitor and arranged in matrix at positions corresponding to the intersections between said plurality of bit-line pairs and said plurality of word lines,
wherein one electrode of said capacitor is connected to a common electrode together with each one electrode of other plurality of capacitors arranged in matrix, and the other electrode of said capacitor is connected to one side of a source-drain path of said transistor, the other side of the source-drain path of said transistor is connected to said bit-line pair, and a gate electrode of said transistor is connected to said word lines,
wherein a circuit for performing writing of memory information to said memory cell, or readout of memory information from said memory cell, or refresh of memory information of said memory cell in response to said plurality of bit-line pairs is connected, and
wherein when a half pitch of said word line is defined as F, the pitch of each bit line of said bit-line pairs is larger than 2F and smaller than 4F.
2. The semiconductor memory device according to claim 1,
wherein each of said bit-line pairs is two bit lines adjacent to each other.
3. The semiconductor memory device according to claim 1,
wherein each of said bit-line pairs is two bit lines not adjacent to each other.
4. The semiconductor memory device according to claim 1,
wherein said capacitor is formed above said bit-line pairs via an insulating film.
5. The semiconductor memory device according to claim 1 or 4,
wherein an active region in a substrate, on which a source, channel and drain of said transistor are formed, is obliquely formed relative to a direction of said bit line pairs.
6. The semiconductor memory device according to claim 1,
wherein a wiring layer for forming each of said word lines is formed of a laminated film of polysilicon and metal or a metal film.
7. The semiconductor memory device according to claim 1,
wherein a wiring layer for forming each of said bit-line pairs is formed of a metal film.
8. The semiconductor memory device according to claim 1,
wherein each of said word lines includes: a main word line with a first length; and a secondary word line with a second length, which is shorter than said main word line and is driven by a driving circuit receiving a signal of said main word line and constitutes the gate electrode of said transistor.
9. The semiconductor memory device according to claim 1,
wherein said word line includes a first wiring layer for forming the gate electrode of said transistor and a second wiring layer which is different from said first wiring layer and is connected to said first wiring layer at a plurality of positions.
10. A semiconductor memory device comprising:
a plurality of folded-type bit-line pairs arranged in parallel to each other;
a plurality of word lines crossing at an acute angle to said plurality of bit-line pairs; and
dynamic memory cells each composed of one transistor and one capacitor and arranged in matrix at positions corresponding to intersections between said plurality of bit-line pairs and said plurality of word lines,
wherein one electrode of said capacitor is connected to a common electrode together with each one electrode of other plurality of capacitors arranged in matrix, and the other electrode of said capacitor is connected to one side of a source-drain path of said transistor, the other side of the source-drain path of said transistor is connected to said bit-line pairs, and a gate electrode of said transistor is connected to said word lines,
wherein a circuit for performing writing of memory information to said memory cell, or readout of memory information from said memory cell, or refresh of memory information of said memory cell in response to said plurality of bit-line pairs is connected, and
wherein, when a half pitch of each of said word lines is defined as F, the pitch of each bit line of said bit-line pairs is larger than 2F and smaller than 4F.
11. The semiconductor memory device according to claim 10,
wherein each said bit-line pairs is two bit lines adjacent to each other.
12. The semiconductor memory device according to claim 10,
wherein each of said bit-line pair is two bit lines not adjacent to each other.
13. The semiconductor memory device according to claim 10,
wherein said capacitor is formed above said bit-line pairs via an insulating film.
14. The semiconductor memory device according to claim 10 or 13,
wherein an active region in a substrate, on which a source, channel and drain of said transistor are formed, is obliquely formed relative to a direction of said bit-line pairs.
15. The semiconductor memory device according to claim 10,
wherein a wiring layer for forming each of said word lines is formed of a laminated film of polysilicon and metal, or a metal film.
16. The semiconductor memory device according to claim 10,
wherein a wiring layer for forming each of said bit-line pairs is formed of a metal film.
17. The semiconductor memory device according to claim 10,
wherein each of said word lines includes: a main word line with a first length; and a secondary word line with a second length, which is shorter than said main word line and is driven by a driving circuit receiving a signal of said main word line and constitutes the gate electrode of said transistor.
18. The semiconductor memory device according to claim 10,
wherein each of said word lines includes: a first wiring layer for forming the gate electrode of said transistor; and a second wiring layer which is different from said first wiring layer and is connected to said first wiring layer at a plurality of positions.
19. A semiconductor memory device comprising:
a first and second dynamic memory cells each including one transistor and one capacitor, both of the first and second dynamic memory cells being to be selected;
a bit-line pair;
a sense amplifier connected to said bit-line pair and amplifying a potential of said bit-line pair;
a data-line pair for transmitting the potential of said bit-line pair; and
a switch circuit between said bit-line pair and said data-line pair,
wherein one of said bit-line pair is connected to said first dynamic memory cell and the other of said bit-line pair is connected to said second dynamic memory cell, and
wherein said switch circuit includes a pair of transistors each having a gate connected to said bit-line pair and a source-drain path connected to said data-line pair.
20. A semiconductor memory device comprising:
a first and second dynamic memory cells each including one transistor and one capacitor, both of the first and second dynamic memory cells being to be selected;
a bit line pair;
a sense amplifier connected to said bit-line pair and amplifying a potential of said bit-line pair;
a data-line pair for transmitting the potential of said bit-line pair; and
a switch circuit between said bit-line pair and said data-line pair,
wherein one of said bit-line pair is connected to said first dynamic memory cell and the other of said bit-line pair is connected to said second dynamic memory cell, and
wherein, said switch circuit is controlled so that before said sense amplifier starts amplifying a readout signal read out from said first and second dynamic memory cells, said readout signal starts being transmitted to said data-line pair.
21. The semiconductor memory device according to claim 20,
wherein, before said readout signal read out to said bit-line pair is amplified by said sense amplifier, the signal transmitted to said data-line pair starts being amplified by the amplifier connected to said data line pair.
22. The semiconductor memory device according to claim 19 or 20,
wherein said first and second dynamic memory cells are controlled by the same word line.
23. The semiconductor memory device according to claim 19 or 20,
wherein said first and second dynamic memory cells are controlled by a plurality of word lines.
24. The semiconductor memory device according to claim 19 or 20,
wherein the signal read out from said first and second dynamic memory cells includes complementary data corresponding to a logic 1 and a logic 0.
25. The semiconductor memory device according to claim 21,
wherein said amplifier is composed of a differential amplifier in which a compensation circuit, which operates to compensate characteristic difference in a pair transistor receiving a differential input, is added.
26. The semiconductor memory device according to claim 21,
wherein said amplifier is composed of a differential amplifier including a pair transistor, and each gate of said pair transistor is formed in a ring shape to reduce the characteristic difference in said pair transistor receiving a differential input.
27. The semiconductor memory device according to claim 19,
wherein said pair of transistors constitutes a differential amplifier.
28. The semiconductor memory device according to claim 20,
wherein said switch circuit is composed of a differential amplifier.
29. The semiconductor memory device according to claim 27 or 28,
wherein said differential amplifier has a compensation circuit added therein, the compensation circuit operating to compensate the characteristic difference in the pair transistor receiving a differential input.
30. The semiconductor memory device according to claim 27 or 28,
wherein said differential amplifier includes a pair transistor receiving a differential input, and each gate of said pair transistor is formed in a ring shape to reduce the characteristic difference in said pair transistor.
31. The semiconductor memory device according to claim 19 or 20,
wherein said memory cells are arranged in matrix at positions corresponding to the intersections between said bit-line pair and a word line forming a gate electrode of said transistor, and when a half pitch of said word line is defined as F, a pitch of each bit line of said bit-line pair is larger than 2F and smaller than 4F.
32. The semiconductor memory device according to claim 31,
wherein an active region in a substrate, on which a source, channel and drain of each of said transistors are formed, is obliquely formed relative to a direction of said bit-line pair.
33. The semiconductor memory device according to claim 19 or 20,
wherein parasitic capacitance of one bit line of said bit-line pair is five times as large as or less than capacitance of said capacitor.
34. A semiconductor memory device comprising:
a first and second dynamic memory cells each including one transistor and one capacitor, both of the first and second dynamic memory cells being to be selected;
a bit line pair;
a sense amplifier which is connected to said bit-line pair and to which a first voltage and a second voltage smaller than said first voltage are applied to amplify a potential of said bit-line pair in directions of said first voltage and said second voltage;
a data-line pair for transmitting signals of said bit-line pair; and
a switch circuit connected between said bit-line pair and said data-line pair,
wherein one bit line of said bit-line pair is connected to said first dynamic memory cell and the other bit line of said bit line pair is connected to said second dynamic memory cell, and
wherein a level of said first voltage or said second voltage is applied to a back-gate region of said transistor.
35. A semiconductor memory device comprising:
a first and second dynamic memory cells each including one transistor and one capacitor, both of the first and second dynamic memory cells being to be selected;
a bit-line pair;
a sense amplifier which is connected to said bit-line pair and to which a first voltage and a second voltage smaller than said first voltage are applied to amplify a potential of said bit-line pair in directions of said first voltage and said second voltage;
a data-line pair for transmitting signals of said bit-line pair; and
a switch circuit connected between said bit-line pair and said data-line pair,
wherein one bit line of said bit-line pair is connected to said first dynamic memory cell and the other bit line of said bit-line pair is connected to said second dynamic memory cell, and
wherein a voltage lower than said first voltage or higher than said second voltage is applied to a back-gate region of said transistor.
36. A semiconductor memory device comprising:
a first and second dynamic memory cells each including one transistor and one capacitor, both of the first and second dynamic memory cells being to be selected;
a bit-line pair;
a sense amplifier which is connected to said bit-line pair and to which a first voltage and a second voltage smaller than said first voltage are applied to amplify a potential of said bit-line pair in directions of said first voltage and said second voltage;
a data-line pair for transmitting signals of said bit-line pair; and
a switch circuit connected between said bit-line pair and said data-line pair,
wherein one bit line of said bit-line pair is connected to said first dynamic memory cell and the other bit line of said bit-line pair is connected to said second dynamic memory cell,
wherein a level of said second voltage is applied to a back-gate region of said transistor, and
wherein a precharge potential of said bit-line pair is set to said first voltage.
37. A semiconductor memory device comprising:
a first and second dynamic memory cells each including one transistor and one capacitor, both of the first and second dynamic memory cells being to be selected;
a bit-line pair;
a sense amplifier which is connected to said bit-line pair and to which a first voltage and a second voltage smaller than said first voltage are applied to amplify a potential of said bit-line pair in directions of said first voltage and said second voltage;
a data-line pair for transmitting signals of said bit-line pair; and
a switch circuit connected between said bit-line pair and said data-line pair,
wherein one bit line of said bit-line pair is connected to said first dynamic memory cell and the other bit line of said bit-line pair is connected to said second dynamic memory cell,
wherein a voltage higher in level than said second voltage is applied to a back-gate region of said transistor, and
wherein a precharge potential of said bit-line pair is set to said first voltage.
38. The semiconductor memory device according to any one of claims 34, 35, 36 and 37,
wherein said first and second dynamic memory cells are controlled by the same word line.
39. The semiconductor memory device according to any one of claims 34, 35, 36 and 37,
wherein said first and second dynamic memory cells are controlled by a plurality of word lines.
40. The semiconductor memory device according to any one of claims 34, 35, 36, and 37,
wherein said memory cells are arranged in matrix at positions corresponding to the intersections between said bit-line pair and a word line forming a gate electrode of said transistor, and when a half pitch of said word line is defined as F, a pitch of each bit line of said bit-line pair is larger than 2F and smaller than 4F.
41. The semiconductor memory device according to claim 40,
wherein an active region in a substrate, on which a source, channel and drain of said transistor are formed, is obliquely formed relative to a direction of said bit-line pair.
42. The semiconductor memory device according to any one of claims 34, 35, 36 and 37,
wherein a potential of a back-gate of a transistor other than those forming said memory cells is set to a level of said second voltage or lower, or a level of said first voltage or higher.
43. A semiconductor memory device comprising:
a dynamic memory cell composed of one transistor and one capacitor;
a bit-line pair to which said memory cell is connected and each bit line of which has parasitic capacitance 2.5 times as large as or lower than said capacitor in capacitance;
a data-line pair transmitting signals of said bit-line pair;
a sense amplifier amplifying a potential of said bit-line pair; and
a pair of MOSFETs, to each gate of which each bit line of said bit-line pair is inputted and each drain of which is connected to the data-line pair.
44. A semiconductor memory device comprising:
a dynamic memory cell composed of one transistor and one capacitor;
a bit-line pair each having parasitic capacitance 2.5 times as large as or lower than said capacitor in capacitance and reading out a signal from said dynamic memory cell; and
a sense amplifier connected to said bit-line pair,
wherein the signal read out to said bit-line pair is transmitted by said sense amplifier to a data line for transmitting a signal of said bit-line pair.