1. A liquid crystal display device including a plurality of liquid crystal display drivers, each of the plurality of liquid crystal display drivers comprising:
a power reception section electrically connected to a battery side, and configured to receive supply of power;
a detection section configured to detect a singular state where a voltage of the battery side has fallen to a value less than or equal to a predetermined voltage value;
a shifting section configured to receive a detection output of the singular state from the detection section to thereby shift to singular control; and
a driver connection section configured to electrically connect the plurality of drivers to each other, wherein,
if the detection section in one of the liquid crystal display drivers has detected the singular state, the shifting section corresponding to the detection section executes the singular control, and the driver connection section corresponding to the detection section notifies the other liquid crystal display driver that the singular state has been detected to thereby cause the singular control of the other driver to be started.
2. The liquid crystal display device according to claim 1, wherein
the one liquid crystal display driver which has detected the singular state earlier than the other is made a master, the other liquid crystal display driver is made a slave, and the driver connection section notifies the other liquid crystal display driver which is the slave of the singularity detection of the master.
3. The liquid crystal display device according to claim 1, wherein
the one of the liquid crystal display drivers which has detected the singular state earlier than the other is already set in advance as the master at the time of power-on, and
setting of the one of the liquid crystal display drivers as the master is carried out on condition that the one the liquid crystal display drivers has detected a threshold of a level higher than a threshold of a low level detected by the other liquid crystal display driver.
4. The liquid crystal display device according to claim 1, wherein
the one of the liquid crystal display drivers is a chip of one integrated circuit, and the other liquid crystal display driver is a plurality of chips of a plurality of integrated circuits.
5. The liquid crystal display device according to claim 1, wherein
as the voltage used by the shifting section to execute the singular control, a voltage of a capacitor of a booster circuit of the liquid crystal display driver is utilized.
6. The liquid crystal display device according to claim 1, wherein
the shifting section writes a signal of a black level to all rows of a liquid crystal display panel all at once as the singular control.
7. The liquid crystal display device according to claim 1, wherein
an application processor configured to supply video data, and a synchronization signal to the plurality of liquid crystal display drivers is connected to the liquid crystal display device.
8. A driving method of a liquid crystal display device, wherein
each of a plurality of liquid crystal display drivers comprises a power reception section configured to receive a power supply from a battery side, a detection section configured to detect a singular state, a shifting section, and a driver connection section configured to electrically connect the plurality of liquid crystal display drivers to each other, the method comprising:
in one of the liquid crystal display drivers,
receiving supply of power from the battery side;
detecting a singular state where a voltage of the battery side has fallen to a value less than or equal to a predetermined voltage value;
executing, if a detection output of the singular state is received, singular control by the shifting section corresponding to the detection section, and
notifying, by the driver connection section, the other liquid crystal display driver that the singular state has been detected to thereby cause the singular control of the other driver to be started.
9. The driving method of a liquid crystal display device according to claim 8, wherein
the shifting section writes a signal of a black level to all rows of a liquid crystal display panel all at once as the singular control.
10. A liquid crystal display device comprising:
a liquid crystal display panel in which two-dimensionally arranged pixel circuits are controlled by a source selection circuit, gate circuits, and a common electrode drive circuit;
a plurality of liquid crystal display drivers electrically connected to a battery side to receive a power supply, and configured to drive the liquid crystal display panel; and
an application processor configured to supply video data, and a synchronization signal to the plurality of liquid crystal display drivers, wherein
each of the plurality of liquid crystal display drivers includes
a power reception section electrically connected to the battery side, and configured to receive the power supply,
a detection section configured to detect a singular state where a voltage of the battery side has fallen to a value less than or equal to a predetermined voltage value,
a shifting section configured to receive a detection output of the singular state from the detection section to thereby shift to singular control, and
a driver connection section configured to electrically connect the plurality of drivers to each other, and
if, in one of the liquid crystal display drivers, the detection section has detected the singular state, the shifting section corresponding to the detection section executes the singular control, and the driver connection section notifies the other liquid crystal display driver that the singular state has been detected to thereby cause the singular control of the other driver to be started.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A rotator comprising:
a rotation circuit;
a first decoder configured to decode a plurality of most significant bits of an input count;
a second decoder configured to decode a plurality of least significant bits of the input count;
a first multiplexor coupled to receive an output of the first decoder in a first order and in a second order, wherein the first order is for left shiftrotate operations and the second order is for right shiftrotate operations;
a first mux select generator circuit configured to generate a first mux select for the first multiplexor responsive to the plurality of least significant bits and a direction of the shiftrotate operation; and
a second multiplexor coupled to receive an output of the second decoder in a third order and in a fourth order, wherein the third order is for left shiftrotate operations and the fourth is order for right shiftrotate operations; and
a second mux select generator circuit configured to generate a second mux select for the second multiplexor responsive to the direction of the shiftrotate operation; and
the first mux select is coupled to a select input of the first multiplexor and the second mux select is coupled to a select input of the second multiplexor; and the rotation circuit is coupled to outputs of the first multiplexor and the second multiplexor and is configured to rotate an input operand to the rotation circuit responsive to the outputs of the first multiplexor and the second multiplexor.
2. The rotator as recited in claim 1 wherein the second order is a reverse bit order of the first order.
3. The rotator as recited in claim 2 wherein the fourth order is the most significant bit of the output of the second decoder concatenated with a reverse bit order of remaining bits of the output of the second decoder.
4. The rotator as recited in claim 1 wherein the first order and the third order are selected in response to a left direction of the shiftrotate operation.
5. The rotator as recited in claim 4 wherein the fourth order is selected in response to a right direction of the shiftrotate operation.
6. The rotator as recited in claim 5 wherein the second order is selected in response to the right direction and further in response to the plurality of least significant bits of the input count not being equal to zero.
7. The rotator as recited in claim 6 wherein the first order is selected in response to the right direction and further in response to the plurality of least significant bits of the input count being equal to zero.
8. A method comprising:
receiving an input operand in a rotation circuit;
decoding a plurality of most significant bits of an input count in a first decoder;
decoding a plurality of least significant bits of the input count in a second decoder;
providing a first order of first decode bits output by the first decoder to the rotation circuit in response to a left shiftrotate operation;
providing a second order of first decode bits output by the first decoder to the rotation circuit in response to a right shiftrotate operation and further in response to the plurality of least significant bits of the input count not being equal to zero; and
rotating the input operand in the rotation circuit at a first granularity responsive to the first decode bits provided in the first order for a left shiftrotate operation and provided in the second order in response to a right shiftrotate operation.
9. The method as recited in claim 8 further comprising:
providing a third order of second decode bits output by the second decoder in response to the left shiftrotate operation;
providing a fourth order of second decode bits output by the second decoder in response to the right shiftrotate operation; and
rotating the input operand previously rotated at the first granularity to a second granularity responsive to the bits provided in the third order in response to the left shiftrotate operation and provided in the fourth order in response to the right shiftrotate operation.
10. The method as recited in claim 9 wherein the second order is a reverse bit ordering of the first order.
11. The method as recited in claim 10 wherein the fourth order is the most significant bit of the output of the second decoder concatenated with a reverse bit order of remaining bits of the output of the second decoder as compared to the third order.
12. The method as recited in claim 8 further comprising providing the first order in response to the right shiftrotate operation and further in response to the plurality of least significant bits of the input count being equal to zero.
13. An apparatus comprising:
a rotation circuit coupled to receive an input operand and provide an output that is rotated according to an input count;
a rotation control circuit configured to decode a plurality of least significant bits of the input count to generate a first rotation control that corresponds to a left direction for the rotation, and wherein the rotation control circuit is configured to concatenate a most significant bit of the first rotation control with a bit-order-reversed order of remaining bits of the first rotation control in response to a right direction for the rotation, and wherein the rotation control circuit is configured to output a bit-level rotation control selected from the first rotation control and the concatenated and bit-reversed first rotation control, and wherein the rotation control circuit is configured to decode a plurality of most significant bits to generate a second rotation control that corresponds to a left direction for the rotation or the plurality of least significant bits of the input count being zero, and wherein the rotation control circuit is configured to generate a bit-reversed-order of the second rotation control that corresponds to the right direction for the rotation and the plurality of least significant bits of the input count being non-zero, and wherein the rotation control circuit is configured to output a byte-level rotation control selected from the second rotation control and the bit-reversed second rotation control; and
wherein the rotation circuit is configured to rotate the input operand at a byte granularity responsive to the byte-level rotation control and at a bit granularity responsive to the bit-level rotation control to provide the output.
14. The apparatus as recited in claim 13 wherein the rotation circuit is configured to perform the byte granularity rotation prior to performing the bit granularity rotation.
15. The apparatus as recited in claim 13 further comprising a mask circuit configured to mask the output of the rotation circuit to produce a shift result, and wherein the mask circuit is configured not to mask the output to produce a rotation result.
16. A processor comprising an execution core configured to perform rotate and shift operations, wherein the execution core comprises a rotator including:
a rotation circuit coupled to receive an input operand and provide an output that is rotated according to an input count;
a rotation control circuit configured to decode a plurality of least significant bits of the input count to generate a first rotation control that corresponds to a left direction for the rotation, and wherein the rotation control circuit is configured to concatenate a most significant bit of the first rotation control with a bit-order-reversed order of remaining bits of the first rotation control in response to a right direction for the rotation, and wherein the rotation control circuit is configured to output a bit-level rotation control selected from the first rotation control and the concatenated and bit-reversed first rotation control, and wherein the rotation control circuit is configured to decode a plurality of most significant bits to generate a second rotation control that corresponds to a left direction for the rotation or the plurality of least significant bits of the input count being zero, and wherein the rotation control circuit is configured to generate a bit-reversed-order of the second rotation control that corresponds to the right direction for the rotation and the plurality of least significant bits of the input count being non-zero, and wherein the rotation control circuit is configured to output a byte-level rotation control selected from the second rotation control and the bit-reversed second rotation control; and
wherein the rotation circuit is configured to rotate the input operand at a byte granularity responsive to the byte-level rotation control and at a bit granularity responsive to the bit-level rotation control to provide the output.
17. The processor as recited in claim 16 wherein the rotation circuit is configured to perform the byte granularity rotation prior to performing the bit granularity rotation.
18. The processor as recited in claim 16 wherein the execution core further comprises a mask circuit configured to mask the output of the rotation circuit to produce a shift result, and wherein the mask circuit is configured not to mask the output to produce a rotation result.