1. A printing method to block dye-migration on a colored synthetic fiber using activated carbon as a component for blocking dye-migration.
2. The method according to claim 1, wherein the activated carbon is incorporated into a composition for blocking dye-migration, and the composition for blocking dye-migration is applied on the position of the fiber to be printed with a desired object.
3. The method according to claim 2, wherein the composition comprises 40\u02dc60 parts of activated carbon, 100 parts of plasticizer, 0.5\u02dc1 parts of epoxy stabilizer, 5\u02dc6 parts of viscosifier and 2\u02dc5 parts of aerosol powder as an additive for film formation, to 100 parts by weight of PVC resin and has viscosity maintained within the range of 20,000\u02dc25,000 cps.
4. The method according to claim 1, wherein printing is performed by using a transfer paper comprising a sheet, a peel-off layer, a printing layer, a resin layer and an adhesive layer, in order from the bottom, wherein the activated carbon is incorporated in the resin layer.
5. The method according to claim 4, wherein the resin layer comprises 30\u02dc50 parts of polyurethane resin, 10\u02dc50 parts of activated carbon and 1\u02dc5 parts of additives, to 100 parts by weight of a solvent.
6. A composition for blocking dye-migration in printing onto colored synthetic fiber comprising activated carbon as an active component.
7. The composition according to claim 6, which comprises 40\u02dc60 parts of activated carbon, 100 parts of plasticizer, 0.5\u02dc1 parts of epoxy stabilizer, 5\u02dc6 parts of viscosifier and 2\u02dc5 parts of aerosol powder as an additive for film formation, to 100 parts by weight of PVC resin and has viscosity maintained within the range of 20,000\u02dc25,000 cps.
8. A transfer paper comprising a sheet, a peel-off layer, a printing layer, a resin layer and an adhesive layer, in order from the bottom, wherein the resin layer comprises activated carbon.
9. The transfer paper according to claim 8, wherein the resin layer comprises 30\u02dc50 parts of polyurethane resin, 10\u02dc50 parts of activated carbon and 1\u02dc5 parts of additives, to 100 parts by weight of a solvent.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit package comprising:
an integrated circuit die comprising N adjacent pads, where N is an integer greater than three;
a substrate comprising a first pair of traces including first and second traces and a second pair of traces including third and fourth traces,
wherein said first, second, third and fourth traces include first ends that are spaced from said integrated circuit die and second ends that are adjacent to said integrated circuit die, wherein said first and second pairs of traces carry differential signals, wherein said third trace of said second pair of traces has a first polarity and said fourth trace of said second pair of traces has a second polarity, and wherein said third trace is located on one side of said fourth trace at said first end and is located on an opposite side of said fourth trace at said second end, wherein said third trace crosses said fourth trace, and wherein said fourth trace comprises a middle section that communicates with said first and second ends of said fourth trace through first and second vias; and
N connections that independently connect said second ends to N pads.
2. The integrated circuit package of claim 1 wherein said N connections comprise N bondwires that connect said second ends to said N pads.
3. The integrated circuit package of claim 2 further comprising a serializerdeserializer (SERDES) module that communicates with said N pads.
4. The integrated circuit package of claim 2 wherein at least one of said N bondwires comprises first and second bondwires that are stacked and connected between at least one of said first, second, third and fourth traces and at least one of said N pads of said integrated circuit die.
5. The integrated circuit package of claim 1 wherein said fourth trace is segmented.
6. The integrated circuit package of claim 5 wherein said fourth trace comprises first and second segments, said first via that passes through said substrate and communicates with said first segment, said second via that passes through said substrate and communicates with said second segment, and said middle section comprising a trace on an opposite side of said substrate that communicates with said first and second vias.
7. The integrated circuit package of claim 6 wherein said third trace comprises a first section, a second section and a middle crossover section that connects said first and second sections.
8. The integrated circuit package of claim 7 wherein said first section is co-linear with said first segment and said second section is co-linear with said second segment.
9. The integrated circuit package of claim 1 wherein said first and second pairs of traces of said substrate carry high speed differential signals.
10. The integrated circuit package of claim 9 wherein said high speed differential signals have a frequency greater than or equal to 1 Gigabit per second (Gbs).
11. The integrated circuit package of claim 1 wherein said second ends of said first and second pairs of traces are spaced at least a first distance from said integrated circuit die and said substrate further comprises fifth and sixth traces that are spaced a second distance from said integrated circuit die, wherein said first distance is greater than said second distance.
12. A network interface comprising the integrated circuit package of claim 1.
13. The network interface of claim 12 wherein said network interface is Ethernet compliant and operates at speeds greater than 1 Gigabit per second.
14. An integrated circuit package comprising:
an integrated circuit die comprising N adjacent pads, where N is an integer greater than three;
a substrate comprising a first pair of traces including first and second traces and a second pair of traces including third and fourth traces,
wherein said first, second, third and fourth traces include first ends that are spaced from said integrated circuit die and second ends that are adjacent to said integrated circuit die, wherein said first and second pairs of traces carry differential signals, wherein said third trace of said second pair of traces has a first polarity and said fourth trace of said second pair of traces has a second polarity, and wherein said third trace is located on one side of said fourth trace at said first end and is located on an opposite side of said fourth trace at said second end; and
N connections that independently connect said second ends to N pads, wherein said third trace crosses said fourth trace, wherein said second end of said third trace is located between said second ends of said fourth trace and said second trace, wherein said third trace crosses said fourth trace, and wherein said fourth trace comprises a middle section that communicates with said first and second ends of said fourth trace through first and second vias.
15. An integrated circuit package comprising:
an integrated circuit die comprising N adjacent pads, where N is an integer greater than three;
a substrate comprising a first pair of traces including first and second traces and a second pair of traces including third and fourth traces,
wherein said first, second, third and fourth traces include first ends that are spaced from said integrated circuit die and second ends that are adjacent to said integrated circuit die, wherein said first and second pairs of traces carry differential signals, wherein said third trace of said second pair of traces has a first polarity and said fourth trace of said second pair of traces has a second polarity, and wherein said third trace is located on one side of said fourth trace at said first end and is located on an opposite side of said fourth trace at said second end; and
N connections that independently connect said second ends to N pads, wherein said third trace crosses said fourth trace, wherein said N connections comprise N bondwires that connect said second ends to said N pads, wherein said second end of said fourth trace is located between said second ends of said third trace and said second trace, wherein said third trace crosses said fourth trace, and wherein said fourth trace comprises a middle section that communicates with said first and second ends of said fourth trace through first and second vias.
16. An integrated circuit package comprising:
an integrated circuit die comprising N adjacent pads, where N is an integer greater than three;
a substrate comprising a first pair of traces including first and second traces and a second pair of traces including third and fourth traces,
wherein said first, second, third and fourth traces include first ends that are spaced from said integrated circuit die and second ends that are adjacent to said integrated circuit die, wherein said first and second pairs of traces carry differential signals, wherein said third trace of said second pair of traces has a first polarity and said fourth trace of said second pair of traces has a second polarity, wherein said third trace is located on one side of said fourth trace at said first end and is located on an opposite side of said fourth trace at said second end, wherein said third trace crosses said fourth trace, wherein said third trace crosses said fourth trace, and wherein said fourth trace comprises a middle section that communicates with said first and second ends of said fourth trace through first and second vias.
N connections that independently connect said second ends to N pads;
fifth and sixth traces;
fifth and sixth pads on said integrated circuit die; and
fifth and sixth bondwires connecting said fifth and sixth traces to said fifth and sixth pads, wherein said N bondwires have a first length and said fifth and sixth bondwires have a second length that is shorter than said first length.
17. An integrated circuit package comprising:
an integrated circuit die comprising N adjacent pads, where N is an integer greater than three;
a substrate comprising a first pair of traces including first and second traces and a second pair of traces including third and fourth traces, wherein said first, second, third and fourth traces include first ends that are spaced from said integrated circuit die and second ends that are adjacent to said integrated circuit die, wherein said first and second pairs of traces carry differential signals, wherein said third trace of said second pair of traces has a first polarity and said fourth trace of said second pair of traces has a second polarity, wherein said third trace is located on one side of said fourth trace at said first end and is located on an opposite side of said fourth trace at said second end, wherein said third trace crosses said fourth trace, and wherein said fourth trace comprises a middle section that communicates with said first and second ends of said fourth trace through first and second vias; and
N connections that independently connect said second ends to N pads, wherein fifth and sixth traces carry signals having a first speed and wherein said first and second pairs of traces carry signals having a second speed that is higher than said first speed.
18. An integrated circuit package comprising:
an integrated circuit die comprising N adjacent pads, where N is an integer greater than three;
a substrate comprising a first pair of traces including first and second traces and a second pair of traces including third and fourth traces,
wherein said first, second, third and fourth traces include first ends that are spaced from said integrated circuit die and second ends that are adjacent to said integrated circuit die, wherein said first and second pairs of traces carry differential signals, wherein said third trace of said second pair of traces has a first polarity and said fourth trace of said second pair of traces has a second polarity, and wherein said third trace is located on one side of said fourth trace at said first end and is located on an opposite side of said fourth trace at said second end; and
N connections that independently connect said second ends to N pads, wherein said substrate includes a first conductive plane and wherein said fourth trace comprises first and second trace segments, a first via that passes through said substrate to said first conductive plane and communicates with said first segment, a second via that passes through said substrate to said first conductive plane and communicates with said second segment, and jumper that is coplanar with and isolated from said first conductive plane and that communicates with said first and second vias.
19. The integrated circuit package of claim 18 wherein said first conductive plane includes one of a ground plane, a signal plane and a power plane.
20. A method of providing an integrated circuit package comprising:
providing N adjacent pads on an integrated circuit die, where N is an integer greater than three;
providing a substrate comprising a first pair of traces including first and second traces and a second pair of traces including third and fourth traces,
locating first ends of said first, second, third and fourth traces spaced from said integrated circuit die;
locating second ends of said first, second, third and fourth traces adjacent to said integrated circuit die;
carrying differential signals using said first and second pairs of traces, wherein said third trace of said second pair of traces has a first polarity and said fourth trace of said second pair of traces has a second polarity;
locating said third trace on one side of said fourth trace at said first end;
locating said third trace on an opposite side of said fourth trace at said second end, wherein said third trace crosses said fourth trace, and wherein said fourth trace comprises a middle section that communicates with said first and second ends of said fourth trace through first and second vias; and
independently connecting said second ends to N pads.
21. The method of claim 20 using N bondwires to connect said second ends to said N pads.
22. The method of claim 21 further comprising:
providing fifth and sixth traces;
providing fifth and sixth pads on said integrated circuit die;
using fifth and sixth bondwires connecting said fifth and sixth traces to said fifth and sixth pads, wherein said N bondwires have a first length and said fifth and sixth bondwires have a second length that is shorter than said first length.
23. The method of claim 21 further comprising a serializerdeserializer (SERDES) module that communicates with said N pads.
24. The method of claim 21 wherein at least one of said N bondwires comprises first and second bondwires that are stacked and connected between at least one of said first, second, third and fourth traces and at least one of said N pads of said integrated circuit die.
25. The method of claim 20 wherein said fourth trace is segmented.
26. The method of claim 25 wherein said fourth trace comprises first and second segments, said first via that passes through said substrate and communicates with said first segment, said second via that passes through said substrate and communicates with said second segment, and said middle section comprising a trace on an opposite side of said substrate that communicates with said first and second vias.
27. The method of claim 26 wherein said third trace comprises a first section, a second section and a middle crossover section that connects said first and second sections.
28. The method of claim 27 wherein said first section is co-linear with said first segment and said second section is co-linear with said second segment.
29. The method of claim 20 further comprising carrying high speed differential signals using said first and second pairs of traces of said substrate.
30. The method of claim 29 wherein said high speed differential signals have a frequency greater than or equal to 1 Gigabit per second (Gbs).
31. The method of claim 20 further comprising:
spacing said second ends of said first and second pairs of traces at least a first distance from said integrated circuit die; and
providing fifth and sixth traces that are spaced a second distance from said integrated circuit die, wherein said first distance is greater than said second distance.
32. The method of claim 31 further comprising:
using said fifth and sixth traces to carry signals having a first speed; and
using said first and second pairs of traces to carry signals having a second speed that is higher than said first speed.
33. The method of claim 20 further comprising implementing a network interface on said integrated circuit die that is Ethernet compliant and operates at speeds greater than 1 Gigabit per second.
34. A method of providing an integrated circuit package comprising:
providing N adjacent pads on an integrated circuit die, where N is an integer greater than three;
providing a substrate comprising a first pair of traces including first and second traces and a second pair of traces including third and fourth traces,
locating first ends of said first, second, third and fourth traces spaced from said integrated circuit die;
locating second ends of said first, second, third and fourth traces adjacent to said integrated circuit die;
carrying differential signals using said first and second pairs of traces, wherein said third trace of said second pair of traces has a first polarity and said fourth trace of said second pair of traces has a second polarity;
locating said third trace on one side of said fourth trace at said first end;
locating said third trace on an opposite side of said fourth trace at said second end; and
independently connecting said second ends to N pads, wherein said third trace crosses said fourth trace, wherein said fourth trace is segmented, wherein said second end of said third trace is located between said second ends of said fourth trace and said second trace, wherein said third trace crosses said fourth trace, and wherein said fourth trace comprises a middle section that communicates with said first and second ends of said fourth trace through first and second vias.
35. A method of providing an integrated circuit package comprising:
providing N adjacent cads on an integrated circuit die, where N is an integer greater than three;
providing a substrate comprising a first pair of traces including first and second traces and a second pair of traces including third and fourth traces,
locating first ends of said first, second, third and fourth traces spaced from said integrated circuit die;
locating second ends of said first, second, third and fourth traces adjacent to said integrated circuit die;
carrying differential signals using said first and second pairs of traces, wherein said third trace of said second pair of traces has a first polarity and said fourth trace of said second pair of traces has a second polarity;
locating said third trace on one side of said fourth trace at said first end;
locating said third trace on an opposite side of said fourth trace at said second end; and
independently connecting said second ends to N pads, wherein said third trace crosses said fourth trace, wherein said fourth trace is segmented, wherein said second end of said fourth trace is located between said second ends of said third trace and said second trace, wherein said third trace crosses said fourth trace, and wherein said fourth trace comprises a middle section that communicates with said first and second ends of said fourth trace through first and second vias.
36. A method of providing an integrated circuit package comprising:
providing N adjacent pads on an integrated circuit die, where N is an integer greater than three;
providing a substrate comprising a first pair of traces including first and second traces and a second pair of traces including third and fourth traces,
locating first ends of said first, second, third and fourth traces spaced from said integrated circuit die;
locating second ends of said first, second, third and fourth traces adjacent to said integrated circuit die;
carrying differential signals using said first and second pairs of traces, wherein said third trace of said second pair of traces has a first polarity and said fourth trace of said second pair of traces has a second polarity;
locating said third trace on one side of said fourth trace at said first end;
locating said third trace on an opposite side of said fourth trace at said second end; and
independently connecting said second ends to N pads, wherein said substrate includes a first conductive plane and wherein said fourth trace comprises first and second trace segments, a first via that passes through said substrate to said first conductive plane and communicates with said first segment, a second via that passes through said substrate to said first conductive plane and communicates with said second segment, and jumper that is coplanar with and isolated from said first conductive plane and that communicates with said first and second visa.
37. The method of claim 36 wherein said first conductive plane includes one of a ground plane, a signal plane and a power plane.