1. A digital-to-analog converter, comprising:
a calibration circuit configured to calibrate a digital-to-analog converter (DAC) element using a residual error from a previously calibrated digital-to-analog converter (DAC) element; and
a calibration error reduction circuit comprising a first memory cell, wherein the residual error is a first residual current error and is at least temporarily stored in the first memory cell, wherein the calibration error reduction circuit further comprises a second memory cell, the second memory cell being configured to store a second residual current error from the DAC element calibrated using the residual error from the previously calibrated DAC element.
2. The converter of claim 1, wherein the calibration error reduction circuit further comprises a charging circuit selectively couplable to the first and second memory cells.
3. The converter of claim 1, wherein the second memory cell is a current source memory.
4. The converter of claim 3, wherein the first memory cell includes a capacitor for storing an electric charge associated with the residual error.
5. A digital-to-analog converter, comprising:
a calibration circuit configured to calibrate a digital-to-analog converter (DAC) element using a residual error from a previously calibrated digital-to-analog converter (DAC) element; and
a calibration error reduction circuit comprising a first memory cell, wherein the residual error is a first residual current error and is at least temporarily stored in the first memory cell,
wherein the calibration error reduction circuit further comprises a charge circuit for storing the residual error in the first memory cell.
6. A method of calibrating a multi-element circuit, the method comprising:
storing a first residual error based on a difference between a reference current and a first calibrated current associated with a first element; and
comparing the reference current and a second calibrated current associated with a second element using the first residual error.
7. The method of claim 6, further comprising:
storing a second residual error based on a comparison of the reference current and the second calibrated current associated with the second element; and
providing the first residual error from a first memory circuit during the comparing step.
8. The method of claim 7, further comprising:
comparing the reference current and a third calibrated current associated with a third element using the second residual error.
9. The method of claim 8, further comprising:
providing the second residual error from a second memory circuit during the second comparing step.
10. The method of claim 8, further comprising:
storing a third residual error associated with a comparison of the reference current and the third calibrated current associated with the third element.
11. The method of claim 10, wherein the third residual error is stored in the first memory circuit.
12. The method of claim 10, wherein a charging circuit effects the storing steps, wherein the charging circuit stores a comparator offset current in the first and second memory circuits.
13. An apparatus, comprising:
means for providing a reference current;
means for providing a first calibrated current in response to a comparison of the reference current and the first calibrated current;
means for storing a first residual error associated with the first calibrated current;
means for providing a second calibrated current in response to a comparison of the reference current and the second calibrated current, the means for providing the second calibrated current using the first residual error; and
means for storing a second residual error associated with the second calibrated current, wherein both means for storing store a comparator offset current.
14. An apparatus, comprising:
means for providing a reference current;
means for providing a first calibrated current in response to a comparison of the reference current and the first calibrated current;
means for storing a first residual error associated with the first calibrated current;
means for providing a second calibrated current in response to a comparison of the reference current and the second calibrated current, the means for providing the second calibrated current using the first residual error; and
means for storing a second residual error associated with the second calibrated current, wherein both means for storing include a current storage circuit.
15. A circuit, comprising:
a plurality of digital-to-analog conversion bit elements, each bit element comprising a calibrated current source; and
a calibration error reduction circuit comprising a first memory circuit, wherein the first memory circuit stores a first residual error associated with a first calibrated current from one of the digital-to-analog conversion bit elements and the first residual error is used to provide a second calibrated current from another of the digital-to-analog conversion bit elements, wherein the calibration error reduction circuit comprises a second memory circuit and stores a second residual error based on a comparison of a reference current and the second calibrated current, wherein the first memory circuit stores a third residual error associated with a third calibrated current from a further of the digital-to-analog conversion bit elements, wherein the second residual error is used to provide the third calibrated current.
16. The circuit of claim 15, wherein the second memory circuit stores a fourth residual error associated with a fourth calibrated current from still another of the digital-to-analog conversion bit elements, wherein the third residual error is used to provide the fourth calibrated current.
17. The circuit of claim 16, wherein integrated nonlinearities associated with calibration errors are reduced by a factor of 2.
18. The circuit of claim 15, wherein the first and second memory circuits are current memory circuits.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method implemented on a computer for pricing a financial derivative of a non-marketed variable xe, the method comprising:
retrieving from a storage medium into memory of the computer information associated with the non-marketed variable xe, and a market representative xm, wherein the market representative xm is useful in determining a value of the financial derivative;
calculating on the computer a solution to an equation involving a price of the financial derivative V(xe, t) defined as a function of xe and time t, wherein the equation comprises a coefficient involving the information associated with xe and xm; and
generating on the computer an output including the calculated price of the financial derivative;
wherein the information associated with xe and xm comprises a drift rate of the non-marketed variable xe, and a drift rate of the market representative xm;
wherein the information associated with xe and xm further comprises variances of the non-marketed variable xe and the market representative xm, and a covariance between the non-marketed variable xe and the market representative xm;
wherein the coefficient involving the information associated with xe and xm has the form \u03bce\u2212\u03b2em(\u03bcm\u2212r), where \u03bce is a drift rate of the non-marketed variable xe, \u03bcm is a drift rate of the market representative xm, and \u03b2em is a factor derived from a variance of the market representative xm and a covariance between the non-marketed variable xe and the market representative xm;
wherein the market representative xm comprises a marketed asset or combination of such assets that is approximately most correlated with the non-marketed variable xe;
wherein the equation is an extended Black-Scholes equation obtained from a standard Black-Scholes equation by replacing, in a term involving a first-order partial derivative of V(xe, t) with respect to xe, a coefficient r, representing an interest rate, by the coefficient involving the information associated with xe and xm.
2. The method of claim 1 wherein the equation is a discrete-time equation involving V(xe, t) defined as a function of xe and discrete time points t=k.
3. The method of claim 1 wherein the market representative xm comprises a combination of multiple marketed assets associated with market sectors most closely associated with the non-marketed variable xe.
4. The method of claim 1 wherein the market representative xm comprises a marketed asset or combination of such assets that is approximately equal to an overall market portfolio.
5. The method of claim 1 further comprising calculating an optimal hedge.
6. The method of claim 1 further comprising calculating a minimum variance of the error between an optimal hedge and the calculated price of the financial derivative.
7. The method of claim 1 wherein the equation represents a risk-neutral discounted expected value of cash flows of the financial derivative.
8. The method of claim 7 wherein a cash flow of the financial derivative is path-dependent.
9. The method of claim 1 applied to derivatives of a set of non-marketed variables wherein the market representative xm comprises a combination of multiple marketed assets, each most-correlated with a different non-marketed variable in the set of non-marketed variables.
10. The method of claim 1 wherein the calculated price of the financial derivative includes cash flows at an intermediate time and a terminal time.
11. The method of claim 1 wherein drift rates, an interest rate, variances, and covariances of xe and xm either vary with time or are governed by stochastic processes.
12. The method of claim 1 wherein the cash flow depends on marketed variables as well as non-marketed variables.
13. The method of claim 1 wherein the equation involves additional non-marketed variables.
14. The method of claim 1 wherein the market representative is derived from a combination of multiple marketed variables, and wherein xe and the multiple marketed variables are governed by either geometric Brownian motion or alternative processes.