1. A flash memory array, comprising:
a matrix of a plurality of flash cell units arranged in a plurality of rows and columns, each of said flash cell units having a drain node and every two adjacent flash cell units in a column having a common source node;
a plurality of word lines, each word line associated with a row of said flash cell units;
a plurality of bit lines laid out perpendicular to said word lines, each bit line associated with a column of said flash cell units and connected to the drains of the flash cell units in the associated column; and
a plurality of source lines laid out in parallel with said word lines, each source line associated with two adjacent rows of said flash cell units having common source nodes and connected to each common source node in the associated rows respectively through a diode;
wherein each flash cell unit is a two-transistor two-bit NAND-based NOR flash cell formed on a triple P-type well, and each row of said flash cell units is associated with two word lines.
2. The flash memory array according to claim 1, wherein each transistor of the flash cell unit comprises:
a gate made of a poly2 conduction layer;
an oxide-nitride-oxide layer underneath said gate;
a floating gate underneath said oxide-nitride-oxide layer; and
a tunneling oxide underneath said floating gate.
3. The flash memory array according to claim 1, wherein an erase operation for selected word lines of said flash memory array is based on a Fowler-Norheim tunneling scheme and accomplished by the following bias condition:
applying a first voltage to said triple P-type well;
applying a second voltage to each of said selected word lines, said first voltage having a voltage level approximately 20V greater than the voltage level of said second voltage;
keeping each bit line as floating; and
keeping each source line as floating.
4. The flash memory array according to claim 1, wherein a program operation in a selected word line of said flash memory array is based on a Fowler-Norheim tunneling scheme and accomplished by the following bias condition:
applying a program voltage to the selected word line, said program voltage being a step-wise pulse voltage in a range from 15V to 20V;
applying a pass voltage of approximately 10V to the other word line in the row associated with the selected word line;
applying a bit-program voltage of 0V to bit lines selected for programming;
applying a bit-inhibit voltage approximately in a range from 8V to 10V to bit lines selected but not to be programmed;
applying an inhibit voltage having a voltage level approximately one half of said bit-inhibit voltage to unselected word lines;
applying a voltage of 0V to the source line in the row associated with the selected word line; and
applying a voltage of 0V to said triple P-type well.
5. The flash memory array according to claim 1, wherein a read operation in a selected word line of said flash memory array is accomplished by the following bias condition:
applying a read voltage to the selected word line, said read voltage being approximately 1.5V to 2V greater than a highest threshold voltage of an erased flash cell unit of said flash memory array;
applying a pass voltage to the other word line in the row associated with the selected word line, said pass voltage being approximately 2greater than a highest threshold voltage of a programmed flash cell unit of said flash memory array;
applying a voltage of approximately 1.5V to the source line in the row associated with the selected word line;
applying a voltage of 0V to unselected word lines; and
applying a voltage of 0V to said triple P-type well.
6. The flash memory array according to claim 1, wherein each source line is made of a metal layer and directly in contact with each common source node which is lightly N\u2212 doped to form a respective Schottky barrier diode, and each bit line is made of another metal layer and connected through a respective ohmic contact to each drain node which is heavily N+doped.
7. The flash memory array according to claim 1, wherein each source line is made of a first metal layer and connected through a respective ohmic contact to each common source node which is lightly N\u2212 doped to form a respective Schottky barrier diode, and each bit line is made of a second metal layer and connected through a first via between said second metal layer and said first metal layer, said first metal layer, and a second via between said first metal layer and each drain node respectively to the drain node which is heavily N+ doped.
8. The flash memory array according to claim 1, wherein each source line is made of a metal layer and connected respectively through a pillar-structured polysilicon diode and a conduction layer to each common source node which is heavily N+ doped, and each bit line is made of another metal layer and connected through a respective ohmic contact to each drain node which is heavily N+doped.
9. The flash memory array according to claim 1, wherein each source line is made of a polysilicon layer and connected respectively through a pillar-structured polysilicon diode and a conduction layer to each common source node which is heavily N+ doped, and each bit line is made of a metal layer and connected through a respective ohmic contact to each drain node which is heavily N+ doped.
10. The flash memory array according to claim 1, wherein each source line is made of a first metal layer and connected through a respective ohmic contact to each common source node which is heavily N+ doped with a PN+ junction diode enclosed therein, and each bit line is made of a second metal layer and connected through a first via between said second metal layer and said first metal layer, said first metal layer, and a second via between said first metal layer and each drain node respectively to the drain node which is heavily N+ doped.
11. The flash memory array according to claim 1, wherein each source line is made of a metal layer and directly in contact with each common source node which is heavily N+ doped with a PN+ junction diode enclosed therein, and each bit line is made of another metal layer and connected through a respective ohmic contact to each drain node which is heavily N+ doped.
12. The flash memory array according to claim 1, wherein each source line is made of a metal layer and directly in contact with each common source node which is lightly N\u2212 doped to form a respective Schottky barrier diode, and each bit line is made of another metal layer and connected through a respective ohmic contact to each drain node which is lightly N\u2212doped with a heavily doped N+ junction region enclosed therein.
13. A flash memory array, comprising:
a matrix of a plurality of flash cell units arranged in a plurality of rows and columns, each of said flash cell units having a drain node and every two adjacent flash cell units in a column having a common source node;
a plurality of word lines, each word line associated with a row of said flash cell units;
a plurality of bit lines laid out perpendicular to said word lines, each bit line associated with a column of said flash cell units and connected to the drains of the flash cell units in the associated column; and
a plurality of source lines laid out in parallel with said word lines, each source line associated with two adjacent rows of said flash cell units having common source nodes and connected to each common source node in the associated rows respectively through a diode;
wherein each flash cell unit is an N transistor NAND-based NOR flash cell formed on a triple P-type well with N being greater than 2, and each row of said flash cell units is associated with N of said word lines.
14. The flash memory array according to claim 13, wherein each transistor of the flash cell unit comprises:
a gate made of a poly2 conduction layer;
an oxide-nitride-oxide layer underneath said gate;
a floating gate underneath said oxide-nitride-oxide layer; and
a tunneling oxide underneath said floating gate.
15. The flash memory array according to claim 13, wherein an erase operation for selected word lines of said flash memory array is based on a Fowler-Norheim tunneling scheme and accomplished by the following bias condition:
applying a first voltage to said triple P-type well;
applying a second voltage to each of said selected word lines, said first voltage having a voltage level approximately 20V greater than the voltage level of said second voltage;
keeping each bit line as floating; and
keeping each source line as floating.
16. The flash memory array according to claim 13, wherein a program operation in a selected word line of said flash memory array is based on a Fowler-Norheim tunneling scheme and accomplished by the following bias condition:
applying a program voltage to the selected word line, said program voltage being a step-wise pulse voltage in a range from 15V to 20V;
applying a pass voltage of approximately 10V to the other word lines in the row associated with the selected word line;
applying a bit-program voltage of 0V to bit lines selected for programming;
applying a bit-inhibit voltage approximately in a range from 8V to 10V to bit lines selected but not to be programmed;
applying an inhibit voltage having a voltage level approximately one half of said bit-inhibit voltage to unselected word lines;
applying a voltage of 0V to the source line in the row associated with the selected word line; and
applying a voltage of 0V to said triple P-type well.
17. The flash memory array according to claim 13, wherein a read operation in a selected word line of said flash memory array is accomplished by the following bias condition:
applying a read voltage to the selected word line, said read voltage being approximately 1.5V to 2V greater than a highest threshold voltage of an erased flash cell unit of said flash memory array;
applying a pass voltage to the other word lines in the row associated with the selected word line, said pass voltage being approximately 2V greater than a highest threshold voltage of a programmed flash cell unit of said flash memory array;
applying a voltage of approximately 1.5V to the source line in the row associated with the selected word line;
applying a voltage of 0V to unselected word lines; and
applying a voltage of 0V to said triple P-type well.
18. The flash memory array according to claim 13, wherein each source line is made of a metal layer and directly in contact with each common source node which is lightly N\u2212 doped to form a respective Schottky barrier diode, and each bit line is made of another metal layer and connected through a respective ohmic contact to each drain node which is heavily N+ doped.
19. The flash memory array according to claim 13, wherein each source line is made of a first metal layer and connected through a respective ohmic contact to each common source node which is lightly N\u2212 doped to form a respective Schottky barrier diode, and each bit line is made of a second metal layer and connected through a first via between said second metal layer and said first metal layer, said first metal layer, and a second via between said first metal layer and each drain node respectively to the drain node which is heavily N+ doped.
20. The flash memory array according to claim 13, wherein each source line is made of a metal layer and connected respectively through a pillar-structured polysilicon diode and a conduction layer to each common source node which is heavily N+ doped, and each bit line is made of another metal layer and connected through a respective ohmic contact to each drain node which is heavily N+ doped.
21. The flash memory array according to claim 13, wherein each source line is made of a polysilicon layer and connected respectively through a pillar-structured polysilicon diode and a conduction layer to each common source node which is heavily N+ doped, and each bit line is made of a metal layer and connected through a respective ohmic contact to each drain node which is heavily N+ doped.
22. The flash memory array according to claim 13, wherein each source line is made of a first metal layer and connected through a respective ohmic contact to each common source node which is heavily N+ doped with a PN+ junction diode enclosed therein, and each bit line is made of a second metal layer and connected through a first via between said second metal layer and said first metal layer, said first metal layer, and a second via between said first metal layer and each drain node respectively to the drain node which is heavily N+ doped.
23. The flash memory array according to claim 13, wherein each source line is made of a metal layer and directly in contact with each common source node which is heavily N+ doped with a PN+ junction diode enclosed therein, and each bit line is made of another metal layer and connected through a respective ohmic contact to each drain node which is heavily N+ doped.
24. The flash memory array according to claim 13, wherein each source line is made of a metal layer and directly in contact with each common source node which is lightly N\u2212 doped to form a respective Schottky barrier diode, and each bit line is made of another metal layer and connected through a respective ohmic contact to each drain node which is lightly N\u2212 doped with a heavily doped N+ junction region enclosed therein.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A wafer container including a container body for supporting a plurality of wafers therein with an opening formed on a sidewall of said container body for importing and exporting said plurality of wafers, a door with an outer surface and an inner surface, said door joining with said opening of said container body via said inner surface, the characteristic of said wafer container in that:
a magnetic member is disposed at inner edge of said opening of said container body and a magnet is disposed on said inner surface of said door corresponding to said magnetic member, said magnet being disposed in a magnetic yoke with recessed cross section; with said magnet of said door attracting said magnetic member at opening of said container body, said door and said container body being lock-fastened to each other.
2. The wafer container according to claim 1, wherein said magnetic member of said container body is selected from the group consisting of: metal material, ceramic material, and polymer material.
3. The wafer container according to claim 1, wherein a first lid is further disposed on said magnetic member of said container body.
4. The wafer container according to claim 1, wherein said magnetic yoke is made of metal material.
5. The wafer container according to claim 1, wherein said magnet of said door includes one outer surface that is not covered by said magnetic yoke, and said outer surface is covered by a pair of lids, a gap being included between said pair of lids for a seal element to be accommodated therein.
6. The wafer container according to claim 1, wherein a recess is disposed on said inner surface by being integrated with said door for separating said inner surface into two platforms, and a restraint module is respectively formed on each of said two platforms, each of said restraint module including a base and a plurality of notches arranged at interval being disposed on said base for contacting said plurality of wafers in said container body.
7. The wafer container according to claim 1, wherein a recess is disposed on said inner surface of said door for separating said inner surface into two platforms and a restraint module is fixedly connected on each of said two platforms respectively, said restraint module including a base and extension of one longer side of said base forming a plurality of suspended arms, a semicircle-like protruding portion being formed between each of said suspended arms and its free end, and a central guide notch being disposed on said protruding portion for contacting said plurality of wafers in said container body.
8. The wafer container according to claim 1, wherein a restriction module is disposed in central area of said inner surface of said door, said restriction module including a base, a plurality of restraint components arranged at interval extending from center of said base to two sides, each of said restraint components including a curve portion and a guide notch being formed at free end of said curve portion for contacting wafer.
9. A wafer container including a container body for supporting a plurality of wafers therein with an opening formed on a sidewall of said container body for importing and exporting said plurality of wafers, a door with an outer surface and an inner surface, said door joining with said opening of said container body via said inner surface, the characteristic of said wafer container in that:
a magnetic yoke with recessed cross section is disposed at inner edge of said opening of said container body, a magnet being disposed in said magnetic yoke and a magnetic member being disposed on said inner surface of said door corresponding to said magnet; with said magnet of said container body attracting said magnetic member of said door, said door and said container body being lock-fastened to each other.
10. The wafer container according to claim 9, wherein said magnetic member of said door is selected from the group consisting of: metal material, ceramic material, and polymer material.
11. The wafer container according to claim 9, wherein said magnetic member of said door corresponds to said magnet with an outer surface and said outer surface is covered by a lid.
12. The wafer container according to claim 9, wherein said magnetic yoke is made of metal material.
13. The wafer container according to claim 9, wherein said magnet of said container body includes one outer surface that is not covered by said magnetic yoke, and said outer surface is covered by a pair of lids, a gap being included between said pair of lids for a seal element to be accommodated therein.
14. The wafer container according to claim 9, wherein a recess is disposed on said inner surface by being integrated with said door for separating said inner surface into two platforms, and a restraint module is respectively formed on each of said two platforms, each of said restraint module including a base and a plurality of notches arranged at interval being disposed on said base for contacting said plurality of wafers in said container body.
15. The wafer container according to claim 9, wherein a recess is disposed on said inner surface of said door for separating said inner surface into two platforms and a restraint module is fixedly connected on each of said two platforms respectively, said restraint module including a base and extension of one longer side of said base forming a plurality of suspended arms, a semicircle-like protruding portion being formed between each of said suspended arms and its free end, and a central guide notch being disposed on said protruding portion for contacting said plurality of wafers in said container body.
16. The wafer container according to claim 9, wherein a restriction module is disposed in central area of said inner surface of said door, said restriction module including a base, a plurality of restraint components arranged at interval extending from center of said base to two sides, each of said restraint components including a curve portion and a guide notch being formed at free end of said curve portion for contacting wafer.
17. A wafer container including a container body for supporting a plurality of wafers therein with an opening formed on a sidewall of said container body for importing and exporting said plurality of wafers, a door with an outer surface and an inner surface, said door joining with said opening of said container body via said inner surface, the characteristic of said wafer container in that:
a magnetic member is disposed at inner edge of said opening of said container body and a magnet is disposed on said inner surface of said door corresponding to said magnetic member, said magnet being disposed in a magnetic yoke with recessed cross section and said door being mixed with metal particles; with design of which said magnet of said door attracting said magnetic member at opening of said container body for said door and said container body to be lock-fastened to each other.
18. The wafer container according to claim 17, wherein said magnetic member of said door is selected from the group consisting of: metal material, ceramic material, and polymer material.
19. The wafer container according to claim 17, wherein said magnetic member of said container body corresponds to said magnet with an outer surface and said outer surface is covered by a lid.
20. The wafer container according to claim 17, wherein said magnetic yoke is made of metal material.