1. An input buffer circuit, comprising:
an input buffer configured to draw an operating current, wherein the operating current is a current sufficient for normal operation of the input buffer;
first buffer enabling circuitry comprising one or more transistors and operatively coupled to a power supply node of the input buffer and configured to cause the input buffer to receive a portion of the operating current when the first buffer enabling circuitry receives an enable signal, wherein the one or more transistors of the first buffer enabling circuitry are responsive to the enable signal; and
second buffer enabling circuitry comprising one or more transistors and operatively coupled to the power supply node of the input buffer and configured to cause the input buffer to receive the operating current when the input buffer is expecting data, wherein the one or more transistors of the second buffer enabling circuitry are responsive to the enable signal.
2. The input buffer circuit of claim 1, wherein the first buffer enabling circuitry causes the input buffer to receive the portion of the operating current during periods of normal operation of the input buffer.
3. The input buffer circuit of claim 1, wherein the input buffer is configured to latch data on a first transition of a CLOCK signal.
4. The input buffer circuit of claim 3, wherein the second buffer enabling circuitry is configured to withhold all but the portion of the operating current from the input buffer responsive to the first transition of the CLOCK signal.
5. The input buffer circuit of claim 3, wherein the second buffer enabling circuitry is configured to cause the input buffer to receive the operating current responsive to a second transition of the CLOCK signal.
6. An input buffer circuit, comprising:
an input buffer configured to draw an operating current, wherein the operating current is a current sufficient for normal operation of the input buffer;
first buffer enabling circuitry comprising one or more transistors and operatively coupled to a power supply node of the input buffer and configured to cause the input buffer to receive a portion of the operating current when the first buffer enabling circuitry receives an enable signal, wherein the one or more transistors of the first buffer enabling circuitry are responsive to the enable signal; and
second buffer enabling circuitry comprising one or more transistors and operatively coupled to the input buffer, the second buffer enabling circuitry being configured to:
cause the input buffer to receive the operating current; and
withhold all but the portion of the operating current from the input buffer when the input buffer is not expecting data;
wherein the one or more transistors of the second buffer enabling circuitry are responsive to the enable signal.
7. The input buffer circuit of claim 6, wherein the first buffer enabling circuitry causes the input buffer to receive the portion of the operating current during periods of normal operation of the input buffer.
8. The input buffer circuit of claim 6, wherein the input buffer is configured to latch data on a first transition of a CLOCK signal.
9. The input buffer circuit of claim 8, wherein the second buffer enabling circuitry is configured to withhold all but the portion of the operating current from the input buffer responsive to the first transition of the CLOCK signal.
10. The input buffer circuit of claim 8, wherein the second buffer enabling circuitry is configured to cause the input buffer to receive the operating current responsive to a second transition of the CLOCK signal.
11. An electronic device, comprising:
a processor;
a power supply configured to provide power to the processor;
a user input device that receives input from a user and provides the input to the processor;
a display device configured to display information;
a volatile memory device comprising an input buffer circuit, the input buffer circuit comprising:
an input buffer configured to draw an operating current, wherein the operating current is a current sufficient for normal operation of the input buffer;
first buffer enabling circuitry comprising one or more transistors and operatively coupled to a power supply node of the input buffer and configured to cause the input buffer to receive a portion of the operating current when the first buffer enabling circuitry receives an enable signal, wherein the one or more transistors of the first buffer enabling circuitry are responsive to the enable signal; and
second buffer enabling circuitry comprising one or more transistors and operatively coupled to the power supply node of the input buffer and configured to cause the input buffer to receive the operating current when the input buffer is expecting data, wherein the one or more transistors of the second buffer enabling circuitry are responsive to the enable signal.
12. The electronic device of claim 11, wherein the first buffer enabling circuitry causes the input buffer to receive the portion of the operating current during periods of normal operation of the input buffer.
13. The electronic device of claim 11, wherein the input buffer is configured to latch data on a first transition of a CLOCK signal.
14. The electronic device of claim 13, wherein the second buffer enabling circuitry is configured to withhold all but the portion of the operating current from the input buffer responsive to the first transition of the CLOCK signal.
15. The electronic device of claim 13, wherein the second buffer enabling circuitry is configured to cause the input buffer to receive the operating current responsive to a second transition of the CLOCK signal.
16. An electronic device, comprising:
a processor;
a power supply configured to provide power to the processor;
a user input device that receives input from a user and provides the input to the processor;
a display device configured to display information;
a volatile memory device comprising an input buffer circuit, the input buffer circuit comprising:
an input buffer configured to draw an operating current, wherein the operating current is a current sufficient for normal operation of the input buffer;
first buffer enabling circuitry comprising one or more transistors and operatively coupled to a power supply node of the input buffer and configured to cause the input buffer to receive a portion of the operating current when the first buffer enabling circuitry receives an enable signal, wherein the one or more transistors of the first buffer enabling circuitry are responsive to the enable signal; and
second buffer enabling circuitry comprising one or more transistors and operatively coupled to the input buffer, the second buffer enabling circuitry being configured to:
cause the input buffer to receive the operating current; and
withhold all but the portion of the operating current from the input buffer when the input buffer is not expecting data;
wherein the one or more transistors of the second buffer enabling circuitry are responsive to the enable signal.
17. The electronic device of claim 16, wherein the first buffer enabling circuitry causes the input buffer to receive the portion of the operating current during periods of normal operation of the input buffer.
18. The electronic device of claim 16, wherein the input buffer is configured to latch data on a first transition of a CLOCK signal.
19. The electronic device of claim 18, wherein the second buffer enabling circuitry is configured to withhold all but the portion of the operating current from the input buffer responsive to the first transition of the CLOCK signal.
20. The electronic device of claim 18, wherein the second buffer enabling circuitry is configured to cause the input buffer to receive the operating current responsive to a second transition of the CLOCK signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A navigation system configured to transmit from a server information concerning surrounding areas of respective client terminals, when terminal position information, which is transmitted at a predetermined interval individually from the respective client terminals, is received by the server,
wherein the server is configured to:
include a terminal position storage device configured to sequentially update and store the respective terminal position information when the respective terminal position information is received from the respective client terminals;
when occurrence of an emergency situation is recognized, divide a region that is affected by the emergency situation into a plurality of areas to which priority levels are given for each degree of influence of the emergency situation thereon;
retrieve from the terminal position storage device positions of the client terminals that reside within the divided areas;
prioritize the client terminal positioned within an area for which the degree of influence is large, and deliver immediately and simultaneously thereto information relating to the emergency situation, regardless of time at which the terminal position information therefrom was received; and
forcibly display the information relating to the emergency situation on a monitor of the client terminal to which the information was delivered.
2. The navigation system according to claim 1, wherein the server is configured to:
when the occurrence of the emergency situation is recognized, aggregate a number of the client terminals that reside internally within each of the divided areas as to latest updated positions of the client terminals; and
in a case that a number of deliveries from the server to the respective client terminals exceeds a predetermined number for which simultaneous delivery is possible, divide the number of deliveries into a plurality of times within a range of the predetermined number, prioritize the client terminals positioned within the area for which the degree of influence is large, and deliver simultaneously thereto the information relating to the emergency situation.
3. The navigation system according to claim 1, wherein the server is configured to set each of the client terminals, for which the respective terminal position information therefor that is stored in the terminal position storage device has not been updated even though a preset time has elapsed, as an object to be excluded from those retrieved from the server.
4. The navigation system according to claim 1, wherein:
when the occurrence of the emergency situation is recognized, and upon dividing the region that is affected by the emergency situation into a plurality of areas to which priority levels are given for each degree of influence of the emergency situation thereon, retrieving from the terminal position storage device the terminal position information of the respective client terminals that reside within each of the areas, prioritizing the client terminal that resides within the area for which the degree of influence is large, and delivering simultaneously thereto the information relating to the emergency situation, and
in addition, when a warning or advisory is set for the region that is affected by the emergency situation, the server is configured to determine a priority ranking for the simultaneous delivery, based on a priority level of the warning or the advisory, and a priority level of the area.