1. A method of recognizing a process in a full-system Industry Standard Architecture emulator, comprising the steps of:
recognizing a process based on a base address of a page table of the process;
recognizing a switch between the processes when said base address of page table changes; and
recognizing termination of a recorded process when the base address of a page table of a process which tries to modify the page table is not equal to the base address of the page table of the recorded process in the page table.
2. The method according to claim 1, wherein the page table of said process is recorded in a process database by a value of the base address of said process.
3. The method according to claim 1, wherein said base address of the page table is stored in a register and the changes of said base address of the page table are determined by monitoring the register.
4. The method according to claim 1, wherein said page table is stored in the memory area of a host platform and the memory area is set as a read-only area, exception handler is set by using said emulator, and upon an attempt to modify said page table in said read-only area, the exception handler is triggered to recognize whether the process is terminated.
5. The method according to claim 1, wherein said emulator saves content-based dynamic binary translation based on the method, said saving of translation comprising:
a translation code lookup step, further comprising the steps of: calculating the digestion of a code page, and looking up a process repository of the code page to determine whether the code page has been translated based on the digestion;
and a translation code saving step, further comprising the steps of translating said code page, and saving the translation results in said process repository by said emulator when said code page has not been translated.
6. The method according to claim 5, wherein said process repository is stored in a fast translation cache of a memory of a host platform, said translation results are only executed in the fast translation cache, said process repository is further stored in a permanent cache of the memory of the host platform, and the process repository stored in the permanent cache is a superset of process repositories stored in said fast translation cache.
7. The method according to claim 6, wherein the translation code lookup step further comprises the step of looking up said process repository in said fast translation cache by the base address of the current process repository.
8. The method according to claim 7, further comprising the step of loading said process repository from the permanent cache to the fast translation cache if said process repository has not been found in the fast translation cache.
9. The method according to claim 8, wherein the step of loading the process repository to the fast translation cache comprises the step of looking up the process repository in the permanent cache by the digestion of the code page.
10. The method according to claim 9, wherein the step of looking up the process repository in the permanent cache comprises:
marking all the process repositories to be looked up in the permanent cache as candidate repositories, and determining whether there is a candidate process repository containing the code page by said digestion of the code page,
when there is no process repository containing the code page in the candidate repositories, creating a new process repository for the code page if no temporary process repository has been created for the code page, otherwise, marking the temporary process repository as a new process repository and then loading it to the fast cache,
when there is more than one process repository containing the code page in the candidate repositories, creating a temporary process repository, loading the translation code to the temporary process repository thereby to be loaded to the fast cache, then marking all the process repositories containing the code page as the candidate repositories for the subsequent code page,
when the number of process repository containing code page is one, loading the process repository containing the code page to the fast cache.
11. A full-system Industry Standard Architecture emulating system, comprising:
means for process recognition for recognizing a process based on a base address of a page table of the process;
means for recognizing a switch between the processes when said base address of the page table changes;
means for recognizing the termination of a recorded process when the base address of a page table of a process which tries to modify the page table is not equal to the base address of the page table of the recorded process in the page table;
means for translation code look-up for calculating the digestion of a code page, and looking up a process repository of the code page to determine whether it has been translated based on the digestion; and,
means for translating saved code for translating the code page and then saving the translation results in the process repository when the code page has not been translated.
12. The system according to claim 11, wherein said base address of the page table is saved in a register and the changes of said base address of the page table are determined by monitoring the register.
13. The system according to claim 11, wherein said page table is saved in the storage area of a host platform and the storage area is set as a read-only area, said process recognition means sets an exception handler, and upon an attempt to modify said page table in said read-only area, the exception handler is triggered to recognize whether the process is terminated.
14. The system according to claim 11, wherein said process repository is saved in a fast translation cache of a memory of a host platform, said translation results are only executed in the fast translation cache, said process repository is also saved in a permanent cache of the memory of the host platform, and the process repositories saved in the permanent cache are the superset of those saved in the fast translation cache.
15. The system according to claim 14, further comprising:
means for translation code look-up; and,
means for process repository look-up for looking up the process repository in the permanent cache to load the process repository into the fast translation cache when the process repository has not been found in the fast translation cache.
16. The system according to claim 15, wherein the lookup of the process repository in the permanent cache comprises:
marking all the process repositories to be looked up in the permanent cache as candidate repositories, determining whether there is a candidate repository containing the code page by said digestion of the code page,
when there is no process repository containing the code page in the candidate repositories, creating a new process repository for the code page if no temporary process repository has been created for the code page, otherwise, marking the temporary process repository as a new process repository and then loading it to the fast cache,
when there is more than one process repository containing the code page in the candidate repositories, creating a temporary process repository, loading the translation code to the temporary process repository to be loaded into fast cache, then marking all the process repositories containing the code page as the candidate repositories for the subsequent code page,
when the number of process repositories containing a code page is one, loading the process repository containing the code page to the fast cache.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A power inverter, with the bottom of the housing (1) of the power inverter being configured to be stepped, cooling bodies (10, 11) being disposed on the exterior face of the stepped bottom, at least two printed circuit boards (6, 8) that overlap each other and communicate with the respective one of the cooling bodies (10, 11) through semiconductor components being provided.
2. The power inverter as set forth in claim 1, wherein the height of the cooling bodies (10, 11) for mounting to the stepped bottom is selected so that the cooling bodies (10, 11) form a plane when mounted to the housing (1).
3. A power inverter with at least one cooling body (11a) disposed outside of the housing (1a) and at least two printed circuit boards (6a, 8a) that communicate with the at least one cooling body (11a) through semiconductor elements, the one printed circuit board (6a) overlapping the other printed circuit board (8c) in the housing (1a) at an incline.
4. The power inverter as set forth in claim 3, wherein the inclined printed circuit board (6a) communicates with the at least one cooling body (11a) through a ramp (12).
5. The power inverter as set forth in claim 4, wherein the semiconductor component (9a) is interposed between the ramp (12) and the printed circuit board (6a).
6. The power inverter as set forth in claim 1, wherein the cooling bodies (10, 11) are arranged laterally offset in the housing (1) when viewed from the front.
7. The power inverter as set forth in claim 1, wherein the printed circuit boards (6, 8, 6a, 8a) communicate with a respective one of the cooling bodies (10, 11, 11a) through semiconductor components (9, 9a).
8. The power inverter as set forth in claim 1, wherein the magnetic components (15) are also cooled by the air flowing through the cooling bodies (10, 11, 11a).
9. The power inverter as set forth in claim 1, wherein the cooling bodies (10, 11, 11a) comprise means (21) for fastening to a housing part (20).
10. The power inverter as set forth in claim 9, wherein the housing (1, 1a) comprises a connection region (30) for the cable supply.
11. The power inverter as set forth in claim 1, wherein the connection region (30) comprises at least one pole block (35) with a plurality of terminals.
12. The power inverter as set forth in claim 1, wherein the transition from the connection chamber (30) to the housing (1, 1a) is sealed with rubber collars (39) in the region of the cable passageways.
13. The power inverter as set forth in claim 1, wherein the connection region comprises a wall (31) oriented at an incline and having a sealable opening (32) for the cables (40).
14. The power inverter as set forth in claim 1, wherein the housing (1, 1a, 1b) is configured to be a cast housing, said cast housing (1, 1a, 1b) comprising cooling ribs.