1. A circuit breaker comprising:
separable contacts;
an operating mechanism structured to open and close said separable contacts, said operating mechanism comprising a latch surface; and
a trip mechanism cooperating with said operating mechanism to trip open said separable contacts, said trip mechanism comprising:
a bimetal having a first side and an opposite second side,
a magnetic yoke disposed proximate the first side of said bimetal, and
a magnetic armature pivotally connected to said bimetal and disposed proximate the opposite second side thereof, said magnetic armature having a first side with a surface, an opposite second side, an opening extending from the first side of said magnetic armature to the opposite second side of said magnetic armature, said opening having a latch surface engaging the latch surface of said operating mechanism when said separable contacts are closed or not tripped open,
wherein during magnetic interruption of current flowing through said separable contacts, the first side of said magnetic armature engages the opposite second side of said bimetal,
wherein at least one of said bimetal and said magnetic armature is structured to provide an offset between said bimetal and the surface of the first side of said magnetic armature at the opening of said magnetic armature,
wherein said bimetal includes an opening extending from the first side of said bimetal to the opposite second side of said bimetal at the opening of said magnetic armature, and
wherein said opening of said bimetal is larger than the opening of said magnetic armature.
2. The circuit breaker of claim 1 wherein the opposite second side of said bimetal includes a depressed pocket facing the first side of said magnetic armature at the opening of said magnetic armature.
3. The circuit breaker of claim 1 wherein the opposite second side of said bimetal includes a slot facing the first side of said magnetic armature at the opening of said magnetic armature.
4. The circuit breaker of claim 1 wherein the opposite second side of said bimetal includes a plurality of projections facing and engaging the first side of said magnetic armature, in order to provide said offset.
5. The circuit breaker of claim 1 wherein the first side of said magnetic armature includes a plurality of projections facing and engaging the opposite second side of said bimetal, in order to provide said offset.
6. The circuit breaker of claim 1 wherein said offset is structured such that said magnetic armature cannot tack weld to said bimetal if arc splatter enters the opening of said magnetic armature.
7. The circuit breaker of claim 1 wherein said offset is formed by a depressed pocket, a slot or an opening of said bimetal.
8. The circuit breaker of claim 1 wherein said offset is formed by a plurality of projections from the first side of said magnetic armature.
9. The circuit breaker of claim 1 wherein said offset is formed by a plurality of projections from the opposite second side of said bimetal.
10. A trip mechanism for an operating mechanism of a circuit breaker, said operating mechanism comprising a latch surface, said trip mechanism comprising:
a bimetal having a first side and an opposite second side,
a magnetic yoke disposed proximate the first side of said bimetal, and
a magnetic armature pivotally connected to said bimetal and disposed proximate the opposite second side thereof, said magnetic armature having a first side with a surface, an opposite second side, an opening extending from the first side of said magnetic armature to the opposite second side of said magnetic armature, said opening having a latch surface structured to engage the latch surface of said operating mechanism,
wherein the first side of said magnetic armature is structured to engage the opposite second side of said bimetal,
wherein at least one of said bimetal and said magnetic armature is structured to provide an offset between said bimetal and the surface of the first side of said magnetic armature at the opening of said magnetic armature,
wherein said bimetal includes an opening extending from the first side of said bimetal to the opposite second side of said bimetal at the opening of said magnetic armature, and
wherein said opening of said bimetal is larger than the opening of said magnetic armature.
11. The trip mechanism of claim 10 wherein the opposite second side of said bimetal includes a depressed pocket facing the first side of said magnetic armature at the opening of said magnetic armature.
12. The trip mechanism of claim 10 wherein the opposite second side of said bimetal includes a slot facing the first side of said magnetic armature at the opening of said magnetic armature.
13. The trip mechanism of claim 10 wherein the opposite second side of said bimetal includes a plurality of projections facing and engaging the first side of said magnetic armature, in order to provide said offset.
14. The trip mechanism of claim 10 wherein the first side of said magnetic armature includes a plurality of projections facing and engaging the opposite second side of said bimetal, in order to provide said offset.
15. The trip mechanism of claim 10 wherein said offset is structured such that said magnetic armature cannot tack weld to said bimetal if arc splatter enters the opening of said magnetic armature.
16. The trip mechanism of claim 10 wherein said offset is formed by a depressed pocket, a slot or an opening of said bimetal.
17. The trip mechanism of claim 10 wherein said offset is formed by a plurality of projections from the first side of said magnetic armature.
18. The trip mechanism of claim 10 wherein said offset is formed by a plurality of projections from the opposite second side of said bimetal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method comprising:
receiving an operand to be normalized at a normalization logic circuit, the operand including a plurality of bits;
generating a zero output when a value of the operand is equal to zero; and
when the value is not equal to zero, generating an output value representing a number that is one less than a count of leading bits of the operand.
2. The method of claim 1, further comprising receiving a normalization instruction that is executable by an execution unit of a processor.
3. The method of claim 2, wherein the operand is received after receiving the normalization instruction.
4. The method of claim 1, wherein generating the zero output further comprises:
determining that the received operand has a value of zero; and
generating a logic signal to provide a zero value at an output of a normalization logic circuit.
5. The method of claim 1, wherein generating an output value representing the number that is one less than the count of leading bits of the operand comprises:
extracting a most significant bit from the operand;
shifting remaining bits of the plurality of bits of the operand left by one bit to produce a plurality of shifted bits;
inserting a zero value in a least significant bit of the plurality of shifted bits;
counting a leading number of zeros in the plurality of shifted bits to produce a shift amount; and
masking a most significant bit of the shift amount to produce the output value.
6. The method of claim 5, wherein masking the most significant bit of the shift amount comprises providing the most significant bit to an input of a logical AND gate that includes a second input coupled to a logical zero value.
7. A processor comprising:
an instruction execution unit configured to execute a normalization instruction, the instruction execution unit comprising:
an input adapted to receive an operand comprising a plurality of bits;
a shifter circuit coupled to the input and adapted to shift the plurality of bits left by one bit to produce a plurality of shifted bits; and
a leading bit counting circuit adapted to receive the plurality of shifted bits and to count a number of leading bits of the plurality of shifted bits, the leading bit counting circuit to provide a count representing the number of leading bits minus one to an output.
8. The processor of claim 7, wherein the instruction execution unit further comprises a logic circuit comprising:
a most significant bit extraction circuit coupled to the input and adapted to extract a most significant bit from the operand; and
a plurality of exclusive OR gates, each of the plurality of exclusive OR gates including a first input adapted to receive the most significant bit, a second input adapted to receive a respective one of the plurality of shifted bits, and an output adapted to provide a value of the respective one of the plurality of shifted bits or a complement of the value.
9. The processor of claim 8, wherein the leading bit counting circuit comprises a leading zero counting circuit coupled to the outputs of the plurality of exclusive OR gates, the leading zero counting circuit configured to count a leading number of zeros received from the outputs of the plurality of exclusive OR gates.
10. The processor of claim 9, further comprising a mask circuit adapted to mask a most significant bit of the count representing the number of leading bits minus one.
11. The processor of claim 7, further comprising a control circuit configured to determine when the operand has a value of zero and configured to produce a control signal to provide a zero value at the output.
12. The processor of claim 11, further comprising a zero circuit responsive to the control circuit and adapted to provide a zero value at the output in response to a control signal from the control circuit.
13. The circuit device of claim 7, wherein the shifter circuit comprises a bi-directional shifter circuit.
14. An instruction executable by a processor to normalize an input value, the instruction comprising:
a first instruction executable by an execution unit to determine a value of an input;
a second instruction executable by the execution unit to produce a zero output when the determined value at the input is zero; and
a third instruction executable by the execution unit to generate a normalization amount representing a count of a leading number of bits minus one when the determined value is non-zero.
15. The instruction of claim 14, wherein the zero output or the count is generated in a single instruction cycle of a processor.
16. The instruction of claim 14, wherein the execution unit comprises normalization logic circuitry adapted to produce the zero output and to generate the normalization amount.
17. The normalize amount instruction of claim 14, wherein the count represents a magnitude of the input.
18. A method comprising:
receiving an operand including a plurality of bits at a normalization logic circuit;
shifting the plurality of bits left by one bit to generate a shifted plurality of bits;
inserting a zero value at a least significant bit of the shifted plurality of bits;
counting a leading number of bits in the shifted plurality of bits; and
outputting a count representing the leading number of bits minus one when the received plurality of bits has a non-zero value.
19. The method of claim 18, wherein counting the leading number of bits comprises:
extracting the most significant bit of the received plurality of bits;
complementing the shifted plurality of bits to produce a complemented plurality of bits when a most significant bit of the received plurality of bits has a one value; and
counting a leading number of zeros in the complemented plurality of bits.
20. The method of claim 18, wherein counting the leading number of bits comprises counting a leading number of zeros in the shifted plurality of bits.
21. The method of claim 18, further comprising providing a zero value at an output when the received operand represents a zero value.
22. A processor comprising:
means for receiving an operand including a plurality of bits;
means for generating a zero output when a value of the operand is equal to zero; and
means for generating an output value representing a number that is one less than a count of leading bits of the operand, when the value of the operand is not equal to zero.
23. The processor of claim 22, further comprising means for receiving a normalize instruction that is executable by an execution unit of a processor in a single execution cycle.
24. The processor of claim 22, wherein generating the zero output further comprises:
means for determining a value of the received operand; and
means for generating a logic signal to provide a zero value at an output of an execution unit when the determined value is zero.
25. The processor of claim 22, wherein generating an output value representing the count of leading bits of the operand minus one comprises:
means for extracting a most significant bit from the operand;
means for shifting remaining bits of the operand left by one bit to produce a plurality of shifted bits;
means for inserting a zero value in a least significant bit of the plurality of shifted bits;
means for counting a leading number of zeros in the plurality of shifted bits to produce a shift amount; and
means for masking a most significant bit of the shift amount to produce the count.