1. An azeotropic or azeotrope-like composition consisting essentially of hydrogen fluoride and 2,3-dichloro-3,3-difluoropropene.
2. An azeotropic or azeotrope-like composition which consists essentially of from about 1 to about 80 weight percent hydrogen fluoride and from about 20 to about 99 weight percent 2,3-dichloro-3,3-difluoropropene, which composition has a boiling point of from about 0\xb0 C. to about 60\xb0 C. at a pressure of from about 9 psia to about 65 psia.
3. The composition of claim 2 which consists of hydrogen fluoride and 2,3-dichloro-3,3-difluoropropene.
4. The composition of claim 2 wherein the hydrogen fluoride is present in the amount from about 35 to about 70 weight percent.
5. The composition of claim 2 wherein the hydrogen fluoride is present in the amount from about 58 to about 64 weight percent.
6. The composition of claim 2 wherein the 2,3-dichloro-3,3-difluoropropene is present in the amount from about 30 to about 65 weight percent.
7. The composition of claim 2 wherein the 2,3-dichloro-3,3-difluoropropene is present in the amount from about 36 to about 42 weight percent.
8. The composition of claim 2 having a boiling point of about 0\xb0 C. at a pressure of about 9 psia.
9. The composition of claim 2 having a boiling point of about 25\xb0 C. at a pressure of about 23 psia.
10. The composition of claim 2 having a boiling point of about 60\xb0 C. at a pressure of about 65 psia.
11. The composition of claim 2 having about 61\xb13 weight percent hydrogen fluoride and about 39\xb13 weight percent 2,3-dichloro-3,3-difluoropropene at 24\xb0 C.
12. A method of forming an azeotropic or azeotrope-like composition which comprises forming a blend consisting essentially of from about 1 to about 80 weight percent hydrogen fluoride and from about 20 to about 99 weight percent 2,3-dichloro-3,3-difluoropropene to thereby form an azeotropic or azeotrope-like composition having a boiling point of from about 0\xb0 C. to about 60\xb0 C. at a pressure of from about 9 psia to about 65 psia.
13. The method of claim 12 wherein the composition consists of hydrogen fluoride and 2,3-dichloro-3,3-difluoropropene.
14. The method of claim 12 wherein the hydrogen fluoride is present in an amount of from about 58 to about 64 weight percent.
15. The method of claim 12 wherein the 2,3-dichloro-3,3-difluoropropene is present in the amount from about 36 to about 42 weight percent.
16. The method of claim 12 wherein the composition has a boiling point of about 0\xb0 C. at a pressure of about 9 psia.
17. The method of claim 12 wherein the composition has a boiling point of from about 25\xb0 C. at a pressure of about 23 psia.
18. The method of claim 12 wherein the composition has a boiling point of about 60\xb0 C. at a pressure of about 65 psia.
19. The composition of claim 12 having about 61\xb13 weight percent hydrogen fluoride and about 39\xb13 weight percent 2,3-dichloro-3,3-difluoropropene at 24\xb0 C.
20. A method for removing 2,3-dichloro-3,3-difluoropropene from a mixture containing 2,3-dichloro-3,3-difluoropropene and at least one impurity, which comprises adding hydrogen fluoride to the mixture in an amount sufficient to form an azeotropic or azeotrope-like composition of the 2,3-dichloro-3,3-difluoropropene and the hydrogen fluoride, and thereafter separating the azeotropic composition from the impurity.
21. The method of claim 20 wherein the impurity does not form an azeotropic mixture with 2,3-dichloro-3,3-difluoropropene, hydrogen fluoride or a mixture of 2,3-dichloro-3,3-difluoropropene and hydrogen fluoride.
22. The method of claim 20 wherein the impurity does form an azeotropic mixture with 2,3-dichloro-3,3-difluoropropene, hydrogen fluoride or a mixture of 2,3-dichloro-3,3-difluoropropene and hydrogen fluoride.
23. The process of claim 20 wherein the impurity comprises a halocarbon.
24. The method of claim 20 wherein the impurity is miscible with 2,3-dichloro-3,3-difluoropropene.
25. The method of claim 20 wherein the impurity comprises 1,1,2,3-tetrachloropropene.
26. The method of claim 20 wherein the impurity comprises 2,3,3,3-tetrafluoropropene.
27. The method of claim 20 wherein the impurity comprises 2-chloro-3,3,3-trifluoropropene.
28. The method of claim 20 wherein the impurity comprises 2-chloro-1,1,1,2-tetrafluoropropane.
29. The method of claim 20 wherein the impurity comprises 1,1,1,2,2-pentafluoropropane.
30. The method of claim 20 wherein the impurity comprises 1,2-dichloro-3,3,3-trifluoropropene.
31. The method of claim 20 wherein the impurity comprises 1,1,1,2,3-pentachloropropane.
32. The method of claim 20 wherein the separating is conducted by distillation.
33. The method of claim 20 wherein the azeotropic composition consists essentially of from about 1 to about 80 weight percent hydrogen fluoride and from about 20 to about 99 weight percent 2,3-dichloro-3,3-difluoropropene.
34. The method of claim 20 wherein the azeotropic composition consists essentially of from about 35 to about 70 weight percent hydrogen fluoride and from about 30 to about 65 weight percent 2,3-dichloro-3,3-difluoropropene.
35. The method of claim 20 wherein the azeotropic composition consists essentially of from about 58 to about 64 weight percent hydrogen fluoride and from about 36 to about 42 weight percent 2,3-dichloro-3,3-difluoropropene.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A processor-based method for floor planning an integrated circuit design, comprising:
establishing in a memory arrangement a plurality of physical blocks in response to user input, wherein each physical block has associated data that indicates a physical area of an integrated circuit to be occupied by logic assigned to the physical block;
assigning each logic block of a logic block hierarchy to one of the plurality of physical blocks in response to user input;
in response to assigning a first logic block to one of the physical blocks, traversing the logic block hierarchy beginning at the first logic block and assigning all children logic blocks of the first logic block to the physical block;
creating pins and nets that connect logic blocks assigned to the physical blocks as a function of locations of the physical blocks on the integrated circuit and connections defined by the logic block hierarchy
reassigning, in response to user input, a child logic block of a first logic block that is assigned to a first physical block to a second physical block;
de-assigning the first logic block from the first physical block in response to the first logic block having children logic blocks assigned to different physical blocks;
wherein each physical block has associated data that indicates each logic block assigned to the physical block;
determining from the logic block hierarchy children blocks of the first logic block; and
determining from the physical blocks whether any children logic blocks of the first logic block are assigned to different physical blocks.
2. The method of claim 1, further comprising, in response to reassigning a child logic block of a second logic block from a third physical block to a fourth physical block and in response to all children logic blocks of the second logic block being assigned to the fourth physical block, assigning the second logic block to the fourth physical block.
3. The method of claim 1, wherein assigning includes establishing a corresponding pointer from a physical block to a logic block in the logic block hierarchy for each logic block assigned to the physical block.
4. The method of claim 3, further comprising:
reassigning, in response to user input, a child logic block of a first logic block that is assigned to a first physical block, to a second physical block, removing a pointer from the first physical block to the child block in the logic block hierarchy, and adding a pointer from the second physical block to the child block in the logic block hierarchy; and
removing a pointer from the first physical block to the first logic block in the logic block hierarchy in response to the first logic block having children logic blocks assigned to different physical blocks.
5. The method of claim 4, further comprising:
determining from the logic block hierarchy children blocks of the first logic block; and
determining from pointers from the physical blocks to the logic block hierarchy whether any children logic blocks of the first logic block are assigned to different physical blocks.
6. The method of claim 5, further comprising, in response to reassigning a child logic block of a second logic block from a third physical block to a fourth physical block and in response to all children logic blocks of the second logic block being assigned to the fourth physical block, adding a pointer from the fourth physical block to the second logic block in the logic block hierarchy.
7. A system for floor planning an integrated circuit design, comprising:
a computer display;
a user-input device;
a computing arrangement coupled to the computer display and to the user input device, the computing arrangement configured to,
establish a plurality of physical blocks in response to user input, wherein each physical block has associated data that indicates a physical area of an integrated circuit to be occupied by logic assigned to the physical block;
assign each logic block of a logic block hierarchy to one of the plurality of physical blocks in response to user input;
output to the display representations of the plurality of physical blocks and assigned logic blocks;
in response to assigning a first logic block to one of the physical blocks, traverse the logic block hierarchy beginning at the first logic block and assign all children logic blocks of the first logic block to the physical block;
create pins and nets that connect logic blocks assigned to the physical blocks as a function of locations of the physical blocks on the integrated circuit and connections defined by the logic block hierarchy
reassign a child logic block of a first logic block that is assigned to a first physical block, to a second physical block in response to user input;
de-assign the first logic block from the first physical block in response to the first logic block having children logic blocks assigned to different physical blocks;
wherein each physical block has associated data that indicates each logic block assigned to the physical block;
determine from the logic block hierarchy children blocks of the first logic block; and
determine from the Physical blocks whether any children logic blocks of the first logic block are assigned to different physical blocks.
8. The system of claim 7, wherein the computing arrangement is further configured to, in response to reassignment of a child logic block of a second logic block from a third physical block to a fourth physical block and in response to all children logic blocks of the second logic block being assigned to the fourth physical block, assign the second logic block to the fourth physical block.
9. The system of claim 7, wherein the computing arrangement is further configured to establish a corresponding pointer from a physical block to a logic block in the logic block hierarchy for each logic block assigned to the physical block.
10. The system of claim 9, wherein the computing arrangement is further configured to:
reassign, in response to user input, a child logic block of a first logic block that is assigned to a first physical block, to a second physical block, remove a pointer from the first physical block to the child block in the logic block hierarchy, and add a pointer from the second physical block to the child block in the logic block hierarchy;
remove a pointer from the first physical block to the first logic block in the logic block hierarchy in response to the first logic block having children logic blocks assigned to different physical blocks.
11. The system of claim 10, wherein the computing arrangement is further configured to:
determine from the logic block hierarchy children blocks of the first logic block; and
determine from pointers from the physical blocks to the logic block hierarchy whether any children logic blocks of the first logic block are assigned to different physical blocks.
12. The system of claim 11, wherein the computing arrangement is further configured to, in response to reassigning a child logic block of a second logic block from a third physical block to a fourth physical block and in response to all children logic blocks of the second logic block being assigned to the fourth physical block, adding a pointer from the fourth physical block to the second logic block in the logic block hierarchy.
13. A processor-based method for floor planning an integrated circuit design, comprising:
establishing in a memory arrangement a plurality of physical blocks in response to user input, wherein each physical block has associated data that indicates a physical area of an integrated circuit to be occupied by logic assigned to the physical block;
assigning each logic block of a logic block hierarchy to one of the plurality of physical blocks in response to user input;
in response to assigning a first logic block to one of the physical blocks, traversing the logic block hierarchy beginning at the first logic block and assigning all children logic blocks of the first logic block to the physical block;
creating pins and nets that connect logic blocks assigned to the physical blocks as a function of locations of the physical blocks on the integrated circuit and connections defined by the logic block hierarchy;
wherein assigning includes establishing a corresponding pointer from a physical block to a logic block in the logic block hierarchy for each logic block assigned to the physical block;
reassigning, in response to user input, a child logic block of a first logic block that is assigned to a first physical block, to a second physical block, removing a pointer from the first physical block to the child block in the logic block hierarchy, and adding a pointer from the second physical block to the child block in the logic block hierarchy; and
removing a pointer from the first physical block to the first logic block in the logic block hierarchy in response to the first logic block having children logic blocks assigned to different physical blocks.
14. The method of claim 13, further comprising:
determining from the logic block hierarchy children blocks of the first logic block; and
determining from pointers from the physical blocks to the logic block hierarchy whether any children logic blocks of the first logic block are assigned to different physical blocks.
15. The method of claim 14, further comprising, in response to reassigning a child logic block of a second logic block from a third physical block to a fourth physical block and in response to all children logic blocks of the second logic block being assigned to the fourth physical block, adding a pointer from the fourth physical block to the second logic block in the logic block hierarchy.