1. A method comprising acts of:
generating a plurality of delay signals that are each delayed by a respective delay period with respect to a master clock, wherein the delay periods of the respective delay signals terminate at a different respective times, and wherein the times are equally spaced and span one period of the master clock signal;
selecting from the plurality of delay signals a first delay signal and a second delay signal; and
generating a timing signal having rising edges and falling edges, wherein the rising edges of the timing signal are based on edges of the first delay signal and the falling edges of the timing signal are based on edges of the second delay signal.
2. The method of claim 1, wherein the act of generating the timing signal further includes generating the timing signal for a signal processing channel.
3. The method of claim 1, further comprising an act of providing the timing signal to a CCD signal processing channel.
4. The method of claim 1, wherein:
the act of generating includes generating the timing signal, wherein the rising edges of the timing signal are based on rising edges of the first delay signal and the falling edges of the timing signal are based on rising edges of the second delay signal.
5. The method of claim 1, further comprising an act of:
selecting the first and second delay signals from a plurality of delay signals.
6. The method of claim 5, further comprising an act of:
selecting the first and second delay signals using an external interface.
7. The method of claim 5 or 6, further comprising acts of:
selecting third and fourth delay signals from the plurality of delay signals; and
generating a second timing signal, wherein at least some rising edges of the second timing signal are based on edges of the third delay signal having a third period and a third phase, and at least some falling edges of the second timing signal are based on edges of the fourth delay signal having a fourth period that is substantially the same as the first, second, and third periods, and a fourth phase that is different from the first, second, and third phases.
8. The method of claim 7, further comprising an act of providing the first and second timing signals to a signal processing channel.
9. The method of claim 5, wherein the act of selecting the first and second delay signals from the plurality of delay signals includes selecting the first and second delay signals from the plurality of delay signals based on first and second selector values, respectively.
10. The method of claim 1, wherein one of the plurality of delay signals has a delay period that approximates one period of the master clock signal.
11. The method of claim 1, wherein the master clock has a frequency, and wherein the act of generating a timing signal comprises generating the timing signal such that it has the same frequency as the master clock.
12. A programmable clock synthesizer, comprising:
a delay signal generator comprising a plurality of delay elements connected in series, wherein a master clock signal is input to the plurality of delay elements, wherein each of the plurality of delay elements outputs a respective delay signal of a plurality of delay signals, and wherein a total phase delay of the plurality of delay elements approximates one period of the master clock signal;
a first multiplexer having a first input to receive the plurality of delay signals, a second input to receive a rising edge selector signal that controls the first multiplexer to select a rising edge delay signal from the plurality of delay signals, and an output to provide the rising edge delay signal;
a second multiplexer having a first input to receive the plurality of delay signals, a second input to receive a falling edge selector signal that controls the second multiplexer to select a falling edge delay signal from the plurality of delay signals, and an output to provide the falling edge delay signal; and
an edge-triggered circuit coupled to the outputs of the first and second multiplexers and adapted to generate a synthesized clock signal having rising edges triggered in response to edges of the rising edge delay signal and falling edges triggered in response to edges of the falling edge delay signal.
13. The programmable clock synthesizer of claim 12, further comprising:
a synthesizer output, coupled to a signal processing channel, to transmit the synthesized clock signal to the signal processing channel.
14. The programmable clock synthesizer of claim 13, wherein the signal processing channel is a CCD signal processing channel.
15. The programmable clock synthesizer of claim 12, wherein the edge-triggered circuit comprises:
a first edge-triggered flip-flop that receives the rising edge delay signal;
a second edge-triggered flip-flop that receives the falling edge delay signal; and
an exclusive or gate, coupled to the first and second edge-triggered flip-flops, that outputs the synthesized clock signal.
16. The programmable clock synthesizer of claim 15, wherein:
the output of the first multiplexer is coupled to a clock input of the first edge-triggered flip-flop; and
the output of the second multiplexer is coupled to a clock input of the second edge-triggered flip-flop.
17. The programmable clock synthesizer of claim 16, wherein the first and second edge-triggered flip-flops are D-type flip-flops, and wherein:
a first input of the exclusive or gate is coupled to a D input of the second edge-triggered flip-flop and an inverted output of the first edge-triggered flip-flop; and
a second input of the exclusive or gate is coupled to a D input of the first edge-triggered flip-flop and a non-inverted output of the second edge-triggered flip-flop.
18. The programmable clock synthesizer of claim 12, wherein the edge-triggered circuit comprises:
a third multiplexer having a first input to receive the rising edge delay signal, a second input to receive the falling edge delay signal, and a third input to receive a selector signal to select one of the rising edge delay signal and the falling edge delay signal to be provided to an output of the third multiplexer; and
an edge-triggered flip-flop, coupled to the output of the third multiplexer, that outputs the synthesized clock signal.
19. The programmable clock synthesizer of claim 18, wherein:
the output of the third multiplexer is coupled to a clock input of the edge-triggered flip-flop.
20. The programmable clock synthesizer of claim 19, wherein the edge-triggered flip-flop is a D-type flip-flop, and wherein:
a D input of the edge-triggered flip-flop is coupled to an inverted output of the edge-triggered flip-flop;
a non-inverted output of the edge-triggered flip-flop is coupled to the third input of the third multiplexer; and
the non-inverted output of the edge-triggered flip-flop provides the synthesized clock signal.
21. The programmable clock synthesizer of claim 12, wherein each of the plurality of delay elements generates a phase delay that is approximately equal.
22. The programmable clock synthesizer of claim 12, wherein the master clock signal has a first frequency, the synthesized clock signal has a second frequency, and the first and second frequencies are the same.
23. A programmable clock synthesizer, comprising:
a delay signal generator comprising a plurality of delay elements connected in series, wherein a master clock signal is input to the plurality of delay elements, wherein each of the plurality of delay elements outputs a respective delay signal of a plurality of delay signals, and wherein a total phase delay of the plurality of delay elements approximates one period of the master clock signal;
circuitry for selecting a rising edge delay signal and a falling edge delay signal from the plurality of delay signals; and
an edge-triggered circuit that receives the comprising edge delay signal and the falling edge delay signal, wherein the edge-triggered circuit is adapted to generate a synthesized clock signal having rising edges triggered in response to edges of the rising edge delay signal and falling edges triggered in response to edges of the falling edge delay signal.
24. The programmable clock synthesizer of claim 23, wherein the edge-triggered circuit comprises:
a first edge-triggered flip-flop that receives the rising edge delay signal;
a second edge-triggered flip-flop that receives the falling edge delay signal; and
an exclusive or gate, coupled to the first and second edge-triggered flip-flops, that outputs the synthesized clock signal.
25. The programmable clock synthesizer of claim 24, wherein:
the first edge-triggered flip-flop receives the rising edge delay signal at a clock input of the first edge-triggered flip-flop; and
the second edge-triggered flip-flop receives the falling edge delay signal at a clock input of the second edge-triggered flip-flop.
26. The programmable clock synthesizer of claim 25, wherein the first and second edge-triggered flip-flops are D-type flip-flops, and wherein:
a first input of the exclusive or gate is coupled to a D input of the second edge-triggered flip-flop and an inverted output of the first edge-triggered flip-flop; and
a second input of the exclusive or gate is coupled to a D input of the first edge-triggered flip-flop and a non-inverted output of the second edge-triggered flip-flop.
27. The programmable clock synthesizer of claim 23, wherein the edge-triggered circuit comprises:
a multiplexer having a first input to receive the rising edge delay signal, a second input to receive the falling edge delay signal, and a third input to receive a selector signal to select one of the rising edge delay signal and the falling edge delay signal to be provided to an output of the multiplexer; and
an edge-triggered flip-flop, coupled to the output of the multiplexer, that outputs the synthesized clock signal.
28. The programmable clock synthesizer of claim 27, wherein:
the output of the multiplexer is coupled to a clock input of the edge-triggered flip-flop.
29. The programmable clock synthesizer of claim 28, wherein the edge-triggered flip-flop is a D-type flip-flop, and wherein:
a D input of the edge-triggered flip-flop is coupled to an inverted output of the edge-triggered flip-flop;
a non-inverted output of the edge-triggered flip-flop is coupled to the third input of the multiplexer; and
the non-inverted output of the edge-triggered flip-flop provides the synthesized clock signal.
30. The programmable clock synthesizer of claim 23, wherein each of the plurality of delay elements generates a phase delay that is approximately equal.
31. The programmable clock synthesizer of claim 23, wherein the master clock signal has a first frequency, the synthesized clock signal has a second frequency, and the first and second frequencies are the same.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A vehicle diagnostic and display system, comprising:
a vehicle diagnostic system comprising:
one or more sensors; and
a diagnostic processor that receives a signal from the one or more sensors indicative of a vehicle condition and determines if a warning condition is present based on the signal; and
a vehicle display system comprising:
a first display;
a second display; and
a display processor that displays a visual warning received from the diagnostic processor on only one of the first and second displays.
2. The vehicle diagnostic and display system of claim 1, wherein the display processor determines an operational status of the first display and displays the visual warning on the second display based on the operational status.
3. The vehicle diagnostic and display system of claim 1, wherein the display processor displays the visual warning only on the first display by default.
4. The vehicle diagnostic and display system of claim 3, wherein the first display is a head-up display.
5. The vehicle diagnostic and display system of claim 4, wherein the second display is an instrument cluster display.
6. The vehicle diagnostic and display system of claim 1, wherein the display processor displays vehicle information on both the first and second displays.
7. The vehicle diagnostic and display system of claim 6, wherein the vehicle information includes vehicle speed information.
8. A method of visual warning management within a vehicle, the method comprising:
determining a warning condition is present using sensor inputs and a diagnostic processor;
determining warning information using the diagnostic processor and sending the warning information to a display processor; and
displaying the warning information including a visual warning on only one of a first display or a second display within the vehicle.
9. The method of claim 8 further comprising determining an operational status of the first display.
10. The method of claim 9 comprising displaying the warning information only on the second display based on the operational status of the first display.
11. The method of claim 8, wherein the display processor displays the visual warning only on the first display by default.
12. The method of claim 11, wherein the first display is a head-up display.
13. The method of claim 12, wherein the second display is an instrument cluster display.
14. The method of claim 8 further comprising displaying vehicle information on both the first and second displays.
15. The method of claim 14, wherein the vehicle information includes vehicle speed information.
16. A method of visual warning management within a vehicle, the method comprising:
determining a warning condition is present using sensor inputs and a diagnostic processor; and
displaying a visual warning associated with the warning condition only on a head-up display if the head-up display is operational.
17. The method of claim 16 further comprising determining if the head-up display is operational using a display processor.
18. The method of claim 17 comprising displaying the visual warning on a second display if the head-up display is not operational.
19. The method of claim 18, wherein the second display is an instrument cluster display.
20. The method of claim 18 further comprising displaying vehicle information on both the head-up display and the second display.