1. A clock gating circuit which receives a first clock signal and controls an output of a second clock signal corresponding to the first clock signal in response to a control signal, the clock gating circuit comprising:
a first latch that latches a signal value of the control signal in synchronization with the first clock signal;
a first gate that receives the first clock signal and controls the output of the second clock signal in response to an output signal of the first latch;
a second latch that latches a signal value of the output signal of the first latch in synchronization with the first clock signal, and outputs a latched value; and
a second gate that controls the output of the second latch in response to a test enable signal and the first clock signal,
wherein the first latch and the second latch form a scan path for a scan test.
2. The clock gating circuit according to claim 1, wherein each of the first latch and the second latch latches a signal value of an input signal at a different signal level of the first clock signal.
3. The clock gating circuit according to claim 1, wherein the second gate controls an output of the first clock signal to the second latch in response to the test enable signal for switching between a normal operation mode and a scan test mode.
4. The clock gating circuit according to claim 1, wherein the first gate controls the output of the second clock signal in response to the output signal of the first latch and the test enable signal for switching between a normal operation mode and a scan test mode.
5. The clock gating circuit according to claim 1, further comprising a selector that selects one of the control signal and a scan signal for observing an operation of the first latch, and supplies a selected signal to the first latch.
6. The clock gating circuit according to claim 1, wherein the clock gating circuit serves as a macro cell.
7. The clock gating circuit according to claim 1, wherein the first gate comprises an AND gate.
8. The clock gating circuit according to claim 1, wherein the second gate comprises an AND gate.
9. The clock gating circuit according to claim 1, further comprising a third gate that controls an output of the first gate in response to a test enable signal and the output signal of the first latch.
10. The clock gating circuit according to claim 9, wherein the first gate receives an output of the second gate and a clock signal and outputs to the second clock signal.
11. The clock gating circuit according to claim 9, wherein the third gate comprises an OR gate.
12. A clock gating circuit which receives a first clock signal and controls an output of a second clock signal corresponding to the first clock signal in response to a control signal, the clock gating circuit comprising:
a first gate that receives the first clock signal and a test enable signal;
a first latch that latches a signal value of the control signal in synchronization with the first clock signal;
a second latch that latches a signal value of the output signal of the first latch in synchronization with an output of the first gate, and outputs a latched value;
a second gate that controls an output of the first clock signal corresponding to the first latch in response to the test enable signal; and
a third gate that controls an output of the second clock signal in response to an output of the second gate and the first clock signal.
13. A clock gating circuit which receives a first clock signal and controls an output of a second clock signal corresponding to the first clock signal in response to a control signal, the clock gating circuit comprising:
a first latch that latches a signal value of the control signal in synchronization with the first clock signal;
a first gate that controls an output of the first clock signal corresponding to the first latch in response to the test enable signal;
a second gate that controls the output of the second clock signal in response to an output of the first gate and the first clock signal; and
a second latch that latches a signal value of the output signal of the first latch in synchronization with the first clock signal, and outputs a latched value.
14. The clock gating circuit according to claim 13, further comprising a third gate that controls the output of the second latch in response to a test enable signal and the first clock signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A communication apparatus, including:
a plurality of circuit boards;
a casing to which the plurality of circuits boards are inserted, the casing being configured such that air is controlled to flow in a ventilation direction as one of:
a direction in which air taken in through a first surface of the casing is controlled to flow between the plurality of circuits boards and exhausted to an outside of the communication apparatus through a second surface of the casing opposite to the first surface, and in which the plurality of circuits boards are one of inserted and removed; and
a direction in which air taken in through the second surface is controlled to flow between the plurality of circuit boards and exhausted to the outside through the first surface, and in which the plurality of circuits boards are one of inserted and removed;
a coupling plate being arranged between the first surface and the second surface in the casing, and having ventilation holes for communicating a first space on the first surface side and a second space on the second surface side to each other, the coupling plate having the plurality of circuit boards coupled to a third surface of the coupling plate, which faces the first surface; and
cables routed in a third space defined in the second space excluding fourth spaces in which the ventilation holes are projected on the second surface in the ventilation direction, the cables coupling the plurality of circuit boards to each other on a fourth surface which faces the second surface so that the plurality of circuit boards are communicable to each other.
2. The communication apparatus according to claim 1, further including rocking suppressing means configured to suppress the cables from being rocked by the air flowing through the fourth spaces.
3. The communication apparatus according to claim 2, wherein the rocking suppressing means includes a fixing member configured to fix a halfway portion of each of the cables to the fourth surface.
4. The communication apparatus according to claim 3, wherein the fixing member fixes the halfway portion under a state in which the each of the cables is bent with a bending radius equal to or larger than a predetermined bending radius.
5. The communication apparatus according to claim 2, wherein the rocking suppressing means includes a plate member configured to partition the fourth spaces from the second space.
6. The communication apparatus according to claim 1, wherein the coupling plate includes a wiring layer configured to couple the plurality of circuit boards to each other so that a first signal to be transmitted at a transmission speed lower than a transmission speed of a second signal to be transmitted through the each of the cables is communicable between the plurality of circuit boards.
7. The communication apparatus according to claim 1, further including other cables routed in the third space on the fourth surface that faces the second surface, configured to couple the plurality of circuit boards to each other so that the first signal to be transmitted at the transmission speed lower than the transmission speed of the second signal to be transmitted through the each of the cables is communicable between the plurality of circuit boards.
8. A communication apparatus, including:
a plurality of circuit boards including:
first circuit boards configured to process packets;
second circuit boards configured to control data to be transmitted between the first circuit boards; and
third circuit boards for supplying power to the first circuit boards and the second circuit boards;
a casing to which the plurality of circuits boards are inserted, the casing being configured such that air is controlled to flow in a ventilation direction as one of:
a direction in which air taken in through a first surface of the casing is controlled to flow between the plurality of circuits boards and exhausted to an outside of the communication apparatus through a second surface of the casing opposite to the first surface, and in which the plurality of circuits boards are one of inserted and removed; and
a direction in which air taken in through the second surface is controlled to flow between the plurality of circuit boards and exhausted to the outside through the first surface, and in which the plurality of circuits boards are one of inserted and removed; and
a coupling plate being arranged between the first surface and the second surface in the casing, and having ventilation holes for communicating a first space on the first surface side and a second space on the second surface side to each other, the coupling plate having the first circuit boards and the third circuit boards coupled to a third surface of the coupling plate, which faces the first surface, and the second circuit boards coupled to a fourth surface of the coupling plate, which faces the second surface, so that the data is transmittable between the first circuit boards via the second circuit boards, and that the power is suppliable from the third circuit boards to the first circuit boards and the second circuit boards.
9. The communication apparatus according to claim 8,
wherein the plurality of circuit boards include fourth circuit boards for controlling the first circuit boards, the second circuit boards, and the third circuit boards, and
wherein the fourth circuit boards are coupled to the third surface of the coupling plate so that a control signal is transmittable from the fourth circuit boards to the first circuit boards, the second circuit boards, and the third circuit boards.
10. The communication apparatus according to claim 8, wherein the coupling plate has through-holes for allowing the first circuit boards and the second circuit boards to be coupled to each other so that the data is transmittable between the first circuit boards and the second circuit boards.